KiCad PCB EDA Suite
BOARD_STACKUP Class Reference

this class manage the layers needed to make a physical board they are solder mask, silk screen, copper and dielectric Some other layers, used in fabrication, are not managed here because they are not used to make a physical board itself Note also there are a few other parameters realed to the physical stackup, like finish type, impedance control and a few others More...

#include <class_board_stackup.h>

Public Member Functions

 BOARD_STACKUP ()
 
 BOARD_STACKUP (BOARD_STACKUP &aOther)
 
BOARD_STACKUPoperator= (const BOARD_STACKUP &aOther)
 
 ~BOARD_STACKUP ()
 
std::vector< BOARD_STACKUP_ITEM * > & GetList ()
 
BOARD_STACKUP_ITEMGetStackupLayer (int aIndex)
 
void RemoveAll ()
 Delete all items in list and clear the list. More...
 
int GetCount ()
 
int BuildBoardTicknessFromStackup () const
 
void Add (BOARD_STACKUP_ITEM *aItem)
 Add a new item in stackup layer. More...
 
bool SynchronizeWithBoard (BOARD_DESIGN_SETTINGS *aSettings)
 Synchronize the BOARD_STACKUP_ITEM* list with the board. More...
 
void BuildDefaultStackupList (BOARD_DESIGN_SETTINGS *aSettings, int aActiveCopperLayersCount=0)
 Creates a default stackup, according to the current BOARD_DESIGN_SETTINGS settings. More...
 
void FormatBoardStackup (OUTPUTFORMATTER *aFormatter, BOARD *aBoard, int aNestLevel) const
 Writes the stackup info on board file. More...
 

Static Public Member Functions

static LSET StackupAllowedBrdLayers ()
 

Public Attributes

wxString m_FinishType
 The name of external copper finish. More...
 
bool m_HasDielectricConstrains
 True if some layers have impedance controlled tracks or have specific constrains for micro-wave applications If the board has dielectric constrains, the .gbrjob will contain info about dielectric constrains: loss tangent and Epsilon rel. More...
 
bool m_HasThicknessConstrains
 True if some layers (copper and/or dielectric) have specific thickness. More...
 
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
 If the board has edge connector cards, some constrains can be specifed in job file: BS_EDGE_CONNECTOR_NONE = no edge connector BS_EDGE_CONNECTOR_IN_USE = board has edge connectors BS_EDGE_CONNECTOR_BEVELLED = edge connectors are bevelled. More...
 
bool m_CastellatedPads
 True if castellated pads exist. More...
 
bool m_EdgePlating
 True if the edge board is plated. More...
 

Private Attributes

std::vector< BOARD_STACKUP_ITEM * > m_list
 

Detailed Description

this class manage the layers needed to make a physical board they are solder mask, silk screen, copper and dielectric Some other layers, used in fabrication, are not managed here because they are not used to make a physical board itself Note also there are a few other parameters realed to the physical stackup, like finish type, impedance control and a few others

Definition at line 209 of file class_board_stackup.h.

Constructor & Destructor Documentation

◆ BOARD_STACKUP() [1/2]

BOARD_STACKUP::BOARD_STACKUP ( )

Definition at line 309 of file class_board_stackup.cpp.

310 {
311  m_HasDielectricConstrains = false; // True if some dielectric layers have constrains
312  // (Loss tg and Epison R)
313  m_HasThicknessConstrains = false; // True if some dielectric or copper layers have constrains
315  m_CastellatedPads = false; // True if some castellated pads exist
316  m_EdgePlating = false; // True if edge board is plated
317  m_FinishType = "None"; // undefined finish type
318 }
wxString m_FinishType
The name of external copper finish.
bool m_EdgePlating
True if the edge board is plated.
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
If the board has edge connector cards, some constrains can be specifed in job file: BS_EDGE_CONNECTOR...
bool m_CastellatedPads
True if castellated pads exist.
bool m_HasDielectricConstrains
True if some layers have impedance controlled tracks or have specific constrains for micro-wave appli...
bool m_HasThicknessConstrains
True if some layers (copper and/or dielectric) have specific thickness.

References BS_EDGE_CONNECTOR_NONE, m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, and m_HasThicknessConstrains.

◆ BOARD_STACKUP() [2/2]

BOARD_STACKUP::BOARD_STACKUP ( BOARD_STACKUP aOther)

Definition at line 321 of file class_board_stackup.cpp.

322 {
327  m_EdgePlating = aOther.m_EdgePlating;
328  m_FinishType = aOther.m_FinishType;
329 
330  // All items in aOther.m_list have to be duplicated, because aOther.m_list
331  // manage pointers to these items
332  for( auto item : aOther.m_list )
333  {
334  BOARD_STACKUP_ITEM* dup_item = new BOARD_STACKUP_ITEM( *item );
335  Add( dup_item );
336  }
337 }
wxString m_FinishType
The name of external copper finish.
bool m_EdgePlating
True if the edge board is plated.
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
If the board has edge connector cards, some constrains can be specifed in job file: BS_EDGE_CONNECTOR...
bool m_CastellatedPads
True if castellated pads exist.
bool m_HasDielectricConstrains
True if some layers have impedance controlled tracks or have specific constrains for micro-wave appli...
std::vector< BOARD_STACKUP_ITEM * > m_list
bool m_HasThicknessConstrains
True if some layers (copper and/or dielectric) have specific thickness.
this class manage one layer needed to make a physical board it can be a solder mask,...
void Add(BOARD_STACKUP_ITEM *aItem)
Add a new item in stackup layer.

References Add(), m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, m_HasThicknessConstrains, and m_list.

◆ ~BOARD_STACKUP()

BOARD_STACKUP::~BOARD_STACKUP ( )
inline

Definition at line 248 of file class_board_stackup.h.

248 { RemoveAll(); }
void RemoveAll()
Delete all items in list and clear the list.

References RemoveAll().

Member Function Documentation

◆ Add()

void BOARD_STACKUP::Add ( BOARD_STACKUP_ITEM aItem)
inline

Add a new item in stackup layer.

Definition at line 275 of file class_board_stackup.h.

275 { m_list.push_back( aItem ); }
std::vector< BOARD_STACKUP_ITEM * > m_list

References m_list.

Referenced by BOARD_STACKUP(), BuildDefaultStackupList(), operator=(), PCB_PARSER::parseBoardStackup(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

◆ BuildBoardTicknessFromStackup()

int BOARD_STACKUP::BuildBoardTicknessFromStackup ( ) const
Returns
the board thickness ( in UI) from the thickness of BOARD_STACKUP_ITEM list

Definition at line 381 of file class_board_stackup.cpp.

382 {
383  // return the board thickness from the thickness of BOARD_STACKUP_ITEM list
384  int thickness = 0;
385 
386  for( auto item : m_list )
387  {
388  if( item->IsThicknessEditable() && item->IsEnabled() )
389  thickness += item->GetThickness();
390  }
391 
392  return thickness;
393 }
std::vector< BOARD_STACKUP_ITEM * > m_list

References m_list.

◆ BuildDefaultStackupList()

void BOARD_STACKUP::BuildDefaultStackupList ( BOARD_DESIGN_SETTINGS aSettings,
int  aActiveCopperLayersCount = 0 
)

Creates a default stackup, according to the current BOARD_DESIGN_SETTINGS settings.

Parameters
aSettingsis the current board setting. if nullptr, build a full stackup (with 32 copper layers)
aActiveCopperLayersCountis used only if aSettings == nullptr is the number of copper layers to use to calculate a default dielectric thickness. ((<= 0 to use all copper layers)

Definition at line 489 of file class_board_stackup.cpp.

491 {
492  // Creates a default stackup, according to the current BOARD_DESIGN_SETTINGS settings.
493  // Note: the m_TypeName string is made translatable using _HKI marker, but is not
494  // translated when building the stackup.
495  // It will be used as this in files, and can be translated only in dialog
496  // if aSettings == NULL, build a full stackup (with 32 copper layers)
497  LSET enabledLayer = aSettings ? aSettings->GetEnabledLayers() : StackupAllowedBrdLayers();
498  int copperLayerCount = aSettings ? aSettings->GetCopperLayerCount() : B_Cu+1;
499 
500  // We need to calculate a suitable dielectric layer thickness.
501  // If no settings, and if aActiveCopperLayersCount is given, use it
502  // (If no settings, and no aActiveCopperLayersCount, the full 32 layers are used)
503  int activeCuLayerCount = copperLayerCount;
504 
505  if( aSettings == nullptr && aActiveCopperLayersCount > 0 )
506  activeCuLayerCount = aActiveCopperLayersCount;
507 
508  int brd__thickness = aSettings ? aSettings->GetBoardThickness() : Millimeter2iu( 1.6 );
509  int diel_thickness = brd__thickness -
510  ( BOARD_STACKUP_ITEM::GetCopperDefaultThickness() * activeCuLayerCount );
511 
512  // Take in account the solder mask thickness:
513  int sm_count = ( enabledLayer & LSET( 2, F_Mask, B_Mask) ).count();
514  diel_thickness -= BOARD_STACKUP_ITEM::GetMaskDefaultThickness() * sm_count;
515 
516  int dielectric_idx = 0;
517 
518  // Add silk screen, solder mask and solder paste layers on top
519  if( enabledLayer[F_SilkS] )
520  {
522  item->SetBrdLayerId( F_SilkS );
523  item->SetTypeName( _HKI( "Top Silk Screen" ) );
524  Add( item );
525  }
526 
527  if( enabledLayer[F_Paste] )
528  {
530  item->SetBrdLayerId( F_Paste );
531  item->SetTypeName( _HKI( "Top Solder Paste" ) );
532  Add( item );
533  }
534 
535  if( enabledLayer[F_Mask] )
536  {
538  item->SetBrdLayerId( F_Mask );
539  item->SetTypeName( _HKI( "Top Solder Mask" ) );
540  Add( item );
541  }
542 
543  // Add copper and dielectric layers
544  for( int ii = 0; ii < copperLayerCount; ii++ )
545  {
547  item->SetBrdLayerId( ( PCB_LAYER_ID )ii );
548  item->SetTypeName( KEY_COPPER );
549  Add( item );
550 
551  if( ii == copperLayerCount-1 )
552  {
553  item->SetBrdLayerId( B_Cu );
554  break;
555  }
556 
557  // Add the dielectric layer:
559  item->SetThickness( diel_thickness );
560  item->SetDielectricLayerId( dielectric_idx + 1 );
561 
562  // Display a dielectric default layer name:
563  if( (dielectric_idx & 1) == 0 )
564  {
565  item->SetTypeName( KEY_CORE );
566  item->SetMaterial( "FR4" );
567  }
568  else
569  {
570  item->SetTypeName( KEY_PREPREG );
571  item->SetMaterial( "FR4" );
572  }
573 
574  Add( item );
575  dielectric_idx++;
576  }
577 
578  // Add silk screen, solder mask and solder paste layers on bottom
579  if( enabledLayer[B_Mask] )
580  {
582  item->SetBrdLayerId( B_Mask );
583  item->SetTypeName( _HKI( "Bottom Solder Mask" ) );
584  Add( item );
585  }
586 
587  if( enabledLayer[B_Paste] )
588  {
590  item->SetBrdLayerId( B_Paste );
591  item->SetTypeName( _HKI( "Bottom Solder Paste" ) );
592  Add( item );
593  }
594 
595  if( enabledLayer[B_SilkS] )
596  {
598  item->SetBrdLayerId( B_SilkS );
599  item->SetTypeName( _HKI( "Bottom Silk Screen" ) );
600  Add( item );
601  }
602 
603  // Transfer other stackup settings from aSettings
604  if( aSettings )
605  {
606  BOARD_STACKUP& source_stackup = aSettings->GetStackupDescriptor();
609  m_CastellatedPads = source_stackup.m_CastellatedPads;
610  m_EdgePlating = source_stackup.m_EdgePlating;
611  m_FinishType = source_stackup.m_FinishType;
612  }
613 }
void SetBrdLayerId(PCB_LAYER_ID aBrdLayerId)
void SetTypeName(const wxString &aName)
this class manage the layers needed to make a physical board they are solder mask,...
wxString m_FinishType
The name of external copper finish.
bool m_EdgePlating
True if the edge board is plated.
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
If the board has edge connector cards, some constrains can be specifed in job file: BS_EDGE_CONNECTOR...
bool m_CastellatedPads
True if castellated pads exist.
#define KEY_COPPER
static int GetCopperDefaultThickness()
bool m_HasDielectricConstrains
True if some layers have impedance controlled tracks or have specific constrains for micro-wave appli...
BOARD_STACKUP & GetStackupDescriptor()
PCB_LAYER_ID
A quick note on layer IDs:
LSET is a set of PCB_LAYER_IDs.
static LSET StackupAllowedBrdLayers()
void SetDielectricLayerId(int aLayerId)
void SetMaterial(const wxString &aName, int aDielectricSubLayer=0)
#define KEY_PREPREG
this class manage one layer needed to make a physical board it can be a solder mask,...
void SetThickness(int aThickness, int aDielectricSubLayer=0)
static int GetMaskDefaultThickness()
LSET GetEnabledLayers() const
Function GetEnabledLayers returns a bit-mask of all the layers that are enabled.
#define KEY_CORE
void Add(BOARD_STACKUP_ITEM *aItem)
Add a new item in stackup layer.
static constexpr int Millimeter2iu(double mm)
#define _HKI(x)
int GetCopperLayerCount() const
Function GetCopperLayerCount.

References _HKI, Add(), B_Cu, B_Mask, B_Paste, B_SilkS, BS_ITEM_TYPE_COPPER, BS_ITEM_TYPE_DIELECTRIC, BS_ITEM_TYPE_SILKSCREEN, BS_ITEM_TYPE_SOLDERMASK, BS_ITEM_TYPE_SOLDERPASTE, F_Mask, F_Paste, F_SilkS, BOARD_DESIGN_SETTINGS::GetBoardThickness(), BOARD_STACKUP_ITEM::GetCopperDefaultThickness(), BOARD_DESIGN_SETTINGS::GetCopperLayerCount(), BOARD_DESIGN_SETTINGS::GetEnabledLayers(), BOARD_STACKUP_ITEM::GetMaskDefaultThickness(), BOARD_DESIGN_SETTINGS::GetStackupDescriptor(), KEY_COPPER, KEY_CORE, KEY_PREPREG, m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, Millimeter2iu(), BOARD_STACKUP_ITEM::SetBrdLayerId(), BOARD_STACKUP_ITEM::SetDielectricLayerId(), BOARD_STACKUP_ITEM::SetMaterial(), BOARD_STACKUP_ITEM::SetThickness(), BOARD_STACKUP_ITEM::SetTypeName(), and StackupAllowedBrdLayers().

Referenced by PANEL_SETUP_BOARD_STACKUP::buildLayerStackPanel(), ALTIUM_PCB::ParseBoard6Data(), and SynchronizeWithBoard().

◆ FormatBoardStackup()

void BOARD_STACKUP::FormatBoardStackup ( OUTPUTFORMATTER aFormatter,
BOARD aBoard,
int  aNestLevel 
) const

Writes the stackup info on board file.

Parameters
aFormatteris the OUTPUTFORMATTER used to create the file
aBoardis the board
aNestLevelis the index to nest level to indent the lines in file

Definition at line 617 of file class_board_stackup.cpp.

619 {
620  // Board stackup is the ordered list from top to bottom of
621  // physical layers and substrate used to build the board.
622  if( m_list.empty() )
623  return;
624 
625  aFormatter->Print( aNestLevel, "(stackup\n" );
626  int nest_level = aNestLevel+1;
627 
628  // Note:
629  // Unspecified parameters are not stored in file.
630  for( BOARD_STACKUP_ITEM* item: m_list )
631  {
632  wxString layer_name;
633 
634  if( item->GetBrdLayerId() == UNDEFINED_LAYER )
635  {
636  layer_name.Printf( "dielectric %d", item->GetDielectricLayerId() );
637  }
638  else
639  layer_name = aBoard->GetLayerName( item->GetBrdLayerId() );
640 
641  aFormatter->Print( nest_level, "(layer %s (type %s)",
642  aFormatter->Quotew( layer_name ).c_str(),
643  aFormatter->Quotew( item->GetTypeName() ).c_str() );
644 
645  if( item->IsColorEditable() && IsPrmSpecified( item->GetColor() ) )
646  aFormatter->Print( 0, " (color %s)",
647  aFormatter->Quotew( item->GetColor() ).c_str() );
648 
649  for( int idx = 0; idx < item->GetSublayersCount(); idx++ )
650  {
651  if( idx ) // not for the main (first) layer.
652  {
653  aFormatter->Print( 0, "\n" );
654  aFormatter->Print( nest_level+1, "addsublayer" );
655  }
656 
657  if( item->IsThicknessEditable() )
658  {
659  if( item->GetType() == BS_ITEM_TYPE_DIELECTRIC && item->IsThicknessLocked( idx ) )
660  aFormatter->Print( 0, " (thickness %s locked)",
661  FormatInternalUnits( item->GetThickness( idx ) ).c_str() );
662  else
663  aFormatter->Print( 0, " (thickness %s)",
664  FormatInternalUnits( item->GetThickness( idx ) ).c_str() );
665  }
666 
667  if( item->HasMaterialValue( idx ) )
668  aFormatter->Print( 0, " (material %s)",
669  aFormatter->Quotew( item->GetMaterial( idx ) ).c_str() );
670 
671  if( item->HasEpsilonRValue() && item->HasMaterialValue( idx ) )
672  aFormatter->Print( 0, " (epsilon_r %g)", item->GetEpsilonR( idx ) );
673 
674  if( item->HasLossTangentValue() && item->HasMaterialValue( idx ) )
675  aFormatter->Print( 0, " (loss_tangent %s)",
676  Double2Str(item->GetLossTangent( idx ) ).c_str() );
677  }
678 
679  aFormatter->Print( 0, ")\n" );
680  }
681 
682  // Other infos about board, related to layers and other fabrication specifications
684  aFormatter->Print( nest_level, "(copper_finish %s)\n",
685  aFormatter->Quotew( m_FinishType ).c_str() );
686 
687  aFormatter->Print( nest_level, "(dielectric_constraints %s)\n",
688  m_HasDielectricConstrains ? "yes" : "no" );
689 
691  aFormatter->Print( nest_level, "(edge_connector %s)\n",
692  m_EdgeConnectorConstraints > 1 ? "bevelled": "yes" );
693 
694  if( m_CastellatedPads )
695  aFormatter->Print( nest_level, "(castellated_pads yes)\n" );
696 
697  if( m_EdgePlating )
698  aFormatter->Print( nest_level, "(edge_plating yes)\n" );
699 
700  aFormatter->Print( aNestLevel, ")\n" );
701 }
const wxString GetLayerName(PCB_LAYER_ID aLayer) const
Function GetLayerName returns the name of a layer.
wxString m_FinishType
The name of external copper finish.
bool m_EdgePlating
True if the edge board is plated.
bool IsPrmSpecified(const wxString &aPrmValue)
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
If the board has edge connector cards, some constrains can be specifed in job file: BS_EDGE_CONNECTOR...
bool m_CastellatedPads
True if castellated pads exist.
std::string Double2Str(double aValue)
Helper function Double2Str to print a float number without using scientific notation and no trailing ...
Definition: base_units.cpp:62
bool m_HasDielectricConstrains
True if some layers have impedance controlled tracks or have specific constrains for micro-wave appli...
std::string Quotew(const wxString &aWrapee)
Definition: richio.cpp:472
std::vector< BOARD_STACKUP_ITEM * > m_list
this class manage one layer needed to make a physical board it can be a solder mask,...
int PRINTF_FUNC Print(int nestLevel, const char *fmt,...)
Function Print formats and writes text to the output stream.
Definition: richio.cpp:404
std::string FormatInternalUnits(int aValue)
Function FormatInternalUnits converts aValue from internal units to a string appropriate for writing ...
Definition: base_units.cpp:560

References BS_ITEM_TYPE_DIELECTRIC, Double2Str(), FormatInternalUnits(), BOARD::GetLayerName(), IsPrmSpecified(), m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, m_list, OUTPUTFORMATTER::Print(), OUTPUTFORMATTER::Quotew(), and UNDEFINED_LAYER.

Referenced by PCB_IO::formatSetup().

◆ GetCount()

int BOARD_STACKUP::GetCount ( )
inline
Returns
the number of layers in the stackup

Definition at line 269 of file class_board_stackup.h.

269 { return (int) m_list.size(); }
std::vector< BOARD_STACKUP_ITEM * > m_list

References m_list.

Referenced by GERBER_JOBFILE_WRITER::addJSONMaterialStackup(), and GetStackupLayer().

◆ GetList()

◆ GetStackupLayer()

BOARD_STACKUP_ITEM * BOARD_STACKUP::GetStackupLayer ( int  aIndex)
Returns
a reference to the layer aIndex, or nullptr if not exists

Definition at line 372 of file class_board_stackup.cpp.

373 {
374  if( aIndex < 0 || aIndex >= GetCount() )
375  return nullptr;
376 
377  return GetList()[aIndex];
378 }
std::vector< BOARD_STACKUP_ITEM * > & GetList()

References GetCount(), and GetList().

Referenced by GERBER_JOBFILE_WRITER::addJSONMaterialStackup().

◆ operator=()

BOARD_STACKUP & BOARD_STACKUP::operator= ( const BOARD_STACKUP aOther)

Definition at line 340 of file class_board_stackup.cpp.

341 {
346  m_EdgePlating = aOther.m_EdgePlating;
347  m_FinishType = aOther.m_FinishType;
348 
349  RemoveAll();
350 
351  // All items in aOther.m_list have to be duplicated, because aOther.m_list
352  // manage pointers to these items
353  for( auto item : aOther.m_list )
354  {
355  BOARD_STACKUP_ITEM* dup_item = new BOARD_STACKUP_ITEM( *item );
356  Add( dup_item );
357  }
358 
359  return *this;
360 }
wxString m_FinishType
The name of external copper finish.
bool m_EdgePlating
True if the edge board is plated.
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
If the board has edge connector cards, some constrains can be specifed in job file: BS_EDGE_CONNECTOR...
bool m_CastellatedPads
True if castellated pads exist.
bool m_HasDielectricConstrains
True if some layers have impedance controlled tracks or have specific constrains for micro-wave appli...
std::vector< BOARD_STACKUP_ITEM * > m_list
bool m_HasThicknessConstrains
True if some layers (copper and/or dielectric) have specific thickness.
this class manage one layer needed to make a physical board it can be a solder mask,...
void RemoveAll()
Delete all items in list and clear the list.
void Add(BOARD_STACKUP_ITEM *aItem)
Add a new item in stackup layer.

References Add(), m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, m_HasThicknessConstrains, m_list, and RemoveAll().

◆ RemoveAll()

void BOARD_STACKUP::RemoveAll ( )

Delete all items in list and clear the list.

Definition at line 363 of file class_board_stackup.cpp.

364 {
365  for( auto item : m_list )
366  delete item;
367 
368  m_list.clear();
369 }
std::vector< BOARD_STACKUP_ITEM * > m_list

References m_list.

Referenced by operator=(), ALTIUM_PCB::ParseBoard6Data(), PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow(), and ~BOARD_STACKUP().

◆ StackupAllowedBrdLayers()

static LSET BOARD_STACKUP::StackupAllowedBrdLayers ( )
inlinestatic
Returns
the board layers full mask allowed in the stackup list i.e. the SilkS, Mask, Paste and all copper layers

Definition at line 258 of file class_board_stackup.h.

259  {
260  return LSET( 6, F_SilkS, F_Mask, F_Paste, B_SilkS, B_Mask, B_Paste )
262  }
LSET is a set of PCB_LAYER_IDs.
static LSET InternalCuMask()
Function InternalCuMask() returns a complete set of internal copper layers, which is all Cu layers ex...
Definition: lset.cpp:672
static LSET ExternalCuMask()
Function ExternalCuMask returns a mask holding the Front and Bottom layers.
Definition: lset.cpp:742

References B_Mask, B_Paste, B_SilkS, LSET::ExternalCuMask(), F_Mask, F_Paste, F_SilkS, and LSET::InternalCuMask().

Referenced by BuildDefaultStackupList(), PANEL_SETUP_BOARD_STACKUP::ImportSettingsFrom(), PANEL_SETUP_BOARD_STACKUP::OnLayersOptionsChanged(), PANEL_SETUP_BOARD_STACKUP::PANEL_SETUP_BOARD_STACKUP(), and PANEL_SETUP_BOARD_STACKUP::transferDataFromUIToStackup().

◆ SynchronizeWithBoard()

bool BOARD_STACKUP::SynchronizeWithBoard ( BOARD_DESIGN_SETTINGS aSettings)

Synchronize the BOARD_STACKUP_ITEM* list with the board.

Not enabled layers are removed Missing layers are added

Parameters
aSettings,isthe current board setting.
Returns
true if changes are made

Definition at line 396 of file class_board_stackup.cpp.

397 {
398  bool change = false;
399  // Build the suitable stackup:
400  BOARD_STACKUP stackup;
401  stackup.BuildDefaultStackupList( aSettings );
402 
403  // First, find removed layers:
404  for( BOARD_STACKUP_ITEM* curr_item: m_list )
405  {
406  bool found = false;
407 
408  for( BOARD_STACKUP_ITEM* item: stackup.GetList() )
409  {
410  if( curr_item->GetBrdLayerId() != UNDEFINED_LAYER )
411  {
412  if( item->GetBrdLayerId() == curr_item->GetBrdLayerId() )
413  {
414  found = true;
415  break;
416  }
417  }
418  else // curr_item = dielectric layer
419  {
420  if( item->GetBrdLayerId() != UNDEFINED_LAYER )
421  continue;
422 
423  if( item->GetDielectricLayerId() == curr_item->GetDielectricLayerId() )
424  {
425  found = true;
426  break;
427  }
428  }
429  }
430 
431  if( !found ) // a layer was removed: a change is found
432  {
433  change = true;
434  break;
435  }
436  }
437 
438  // Now initialize all stackup items to the initial values, when exist
439  for( BOARD_STACKUP_ITEM* item: stackup.GetList() )
440  {
441  bool found = false;
442  // Search for initial settings:
443  for( BOARD_STACKUP_ITEM* initial_item: m_list )
444  {
445  if( item->GetBrdLayerId() != UNDEFINED_LAYER )
446  {
447  if( item->GetBrdLayerId() == initial_item->GetBrdLayerId() )
448  {
449  *item = *initial_item;
450  found = true;
451  break;
452  }
453  }
454  else // dielectric layer: see m_DielectricLayerId for identification
455  {
456  // Compare dielectric layer with dielectric layer
457  if( initial_item->GetBrdLayerId() != UNDEFINED_LAYER )
458  continue;
459 
460  if( item->GetDielectricLayerId() == initial_item->GetDielectricLayerId() )
461  {
462  *item = *initial_item;
463  found = true;
464  break;
465  }
466  }
467  }
468 
469  if( !found )
470  {
471  change = true;
472  }
473  }
474 
475  // Transfer other stackup settings from aSettings
476  BOARD_STACKUP& source_stackup = aSettings->GetStackupDescriptor();
479  m_CastellatedPads = source_stackup.m_CastellatedPads;
480  m_EdgePlating = source_stackup.m_EdgePlating;
481  m_FinishType = source_stackup.m_FinishType;
482 
483  *this = stackup;
484 
485  return change;
486 }
std::vector< BOARD_STACKUP_ITEM * > & GetList()
this class manage the layers needed to make a physical board they are solder mask,...
wxString m_FinishType
The name of external copper finish.
bool m_EdgePlating
True if the edge board is plated.
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
If the board has edge connector cards, some constrains can be specifed in job file: BS_EDGE_CONNECTOR...
bool m_CastellatedPads
True if castellated pads exist.
bool m_HasDielectricConstrains
True if some layers have impedance controlled tracks or have specific constrains for micro-wave appli...
BOARD_STACKUP & GetStackupDescriptor()
std::vector< BOARD_STACKUP_ITEM * > m_list
this class manage one layer needed to make a physical board it can be a solder mask,...
void BuildDefaultStackupList(BOARD_DESIGN_SETTINGS *aSettings, int aActiveCopperLayersCount=0)
Creates a default stackup, according to the current BOARD_DESIGN_SETTINGS settings.

References BuildDefaultStackupList(), GetList(), BOARD_DESIGN_SETTINGS::GetStackupDescriptor(), m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, m_list, and UNDEFINED_LAYER.

Referenced by GERBER_JOBFILE_WRITER::addJSONMaterialStackup().

Member Data Documentation

◆ m_CastellatedPads

◆ m_EdgeConnectorConstraints

BS_EDGE_CONNECTOR_CONSTRAINTS BOARD_STACKUP::m_EdgeConnectorConstraints

If the board has edge connector cards, some constrains can be specifed in job file: BS_EDGE_CONNECTOR_NONE = no edge connector BS_EDGE_CONNECTOR_IN_USE = board has edge connectors BS_EDGE_CONNECTOR_BEVELLED = edge connectors are bevelled.

Definition at line 238 of file class_board_stackup.h.

Referenced by BOARD_STACKUP(), BuildDefaultStackupList(), BuildStackupReport(), FormatBoardStackup(), operator=(), PCB_PARSER::parseBoardStackup(), PANEL_SETUP_BOARD_STACKUP::synchronizeWithBoard(), SynchronizeWithBoard(), PANEL_SETUP_BOARD_STACKUP::transferDataFromUIToStackup(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

◆ m_EdgePlating

◆ m_FinishType

◆ m_HasDielectricConstrains

bool BOARD_STACKUP::m_HasDielectricConstrains

True if some layers have impedance controlled tracks or have specific constrains for micro-wave applications If the board has dielectric constrains, the .gbrjob will contain info about dielectric constrains: loss tangent and Epsilon rel.

If not, these values will be not specified in job file.

Definition at line 226 of file class_board_stackup.h.

Referenced by GERBER_JOBFILE_WRITER::addJSONMaterialStackup(), BOARD_STACKUP(), BuildDefaultStackupList(), BuildStackupReport(), FormatBoardStackup(), operator=(), PCB_PARSER::parseBoardStackup(), PANEL_SETUP_BOARD_STACKUP::synchronizeWithBoard(), SynchronizeWithBoard(), PANEL_SETUP_BOARD_STACKUP::transferDataFromUIToStackup(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

◆ m_HasThicknessConstrains

bool BOARD_STACKUP::m_HasThicknessConstrains

True if some layers (copper and/or dielectric) have specific thickness.

Definition at line 230 of file class_board_stackup.h.

Referenced by BOARD_STACKUP(), and operator=().

◆ m_list


The documentation for this class was generated from the following files: