KiCad PCB EDA Suite
BOARD_STACKUP Class Reference

this class manage the layers needed to make a physical board they are solder mask, silk screen, copper and dielectric Some other layers, used in fabrication, are not managed here because they are not used to make a physical board itself Note also there are a few other parameters related to the physical stackup, like finish type, impedance control and a few others More...

#include <class_board_stackup.h>

Public Member Functions

 BOARD_STACKUP ()
 
 BOARD_STACKUP (BOARD_STACKUP &aOther)
 
BOARD_STACKUPoperator= (const BOARD_STACKUP &aOther)
 
 ~BOARD_STACKUP ()
 
std::vector< BOARD_STACKUP_ITEM * > & GetList ()
 
BOARD_STACKUP_ITEMGetStackupLayer (int aIndex)
 
void RemoveAll ()
 Delete all items in list and clear the list. More...
 
int GetCount ()
 
int BuildBoardTicknessFromStackup () const
 
void Add (BOARD_STACKUP_ITEM *aItem)
 Add a new item in stackup layer. More...
 
bool SynchronizeWithBoard (BOARD_DESIGN_SETTINGS *aSettings)
 Synchronize the BOARD_STACKUP_ITEM* list with the board. More...
 
void BuildDefaultStackupList (BOARD_DESIGN_SETTINGS *aSettings, int aActiveCopperLayersCount=0)
 Creates a default stackup, according to the current BOARD_DESIGN_SETTINGS settings. More...
 
void FormatBoardStackup (OUTPUTFORMATTER *aFormatter, BOARD *aBoard, int aNestLevel) const
 Writes the stackup info on board file. More...
 

Static Public Member Functions

static LSET StackupAllowedBrdLayers ()
 

Public Attributes

wxString m_FinishType
 The name of external copper finish. More...
 
bool m_HasDielectricConstrains
 True if some layers have impedance controlled tracks or have specific constrains for micro-wave applications If the board has dielectric constrains, the .gbrjob will contain info about dielectric constrains: loss tangent and Epsilon rel. More...
 
bool m_HasThicknessConstrains
 True if some layers (copper and/or dielectric) have specific thickness. More...
 
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
 If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTOR_NONE = no edge connector BS_EDGE_CONNECTOR_IN_USE = board has edge connectors BS_EDGE_CONNECTOR_BEVELLED = edge connectors are beveled. More...
 
bool m_CastellatedPads
 True if castellated pads exist. More...
 
bool m_EdgePlating
 True if the edge board is plated. More...
 

Private Attributes

std::vector< BOARD_STACKUP_ITEM * > m_list
 

Detailed Description

this class manage the layers needed to make a physical board they are solder mask, silk screen, copper and dielectric Some other layers, used in fabrication, are not managed here because they are not used to make a physical board itself Note also there are a few other parameters related to the physical stackup, like finish type, impedance control and a few others

Definition at line 210 of file class_board_stackup.h.

Constructor & Destructor Documentation

◆ BOARD_STACKUP() [1/2]

BOARD_STACKUP::BOARD_STACKUP ( )

Definition at line 311 of file class_board_stackup.cpp.

312 {
313  m_HasDielectricConstrains = false; // True if some dielectric layers have constrains
314  // (Loss tg and Epison R)
315  m_HasThicknessConstrains = false; // True if some dielectric or copper layers have constrains
317  m_CastellatedPads = false; // True if some castellated pads exist
318  m_EdgePlating = false; // True if edge board is plated
319  m_FinishType = "None"; // undefined finish type
320 }
wxString m_FinishType
The name of external copper finish.
bool m_EdgePlating
True if the edge board is plated.
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTO...
bool m_CastellatedPads
True if castellated pads exist.
bool m_HasDielectricConstrains
True if some layers have impedance controlled tracks or have specific constrains for micro-wave appli...
bool m_HasThicknessConstrains
True if some layers (copper and/or dielectric) have specific thickness.

References BS_EDGE_CONNECTOR_NONE, m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, and m_HasThicknessConstrains.

◆ BOARD_STACKUP() [2/2]

BOARD_STACKUP::BOARD_STACKUP ( BOARD_STACKUP aOther)

Definition at line 323 of file class_board_stackup.cpp.

324 {
329  m_EdgePlating = aOther.m_EdgePlating;
330  m_FinishType = aOther.m_FinishType;
331 
332  // All items in aOther.m_list have to be duplicated, because aOther.m_list
333  // manage pointers to these items
334  for( auto item : aOther.m_list )
335  {
336  BOARD_STACKUP_ITEM* dup_item = new BOARD_STACKUP_ITEM( *item );
337  Add( dup_item );
338  }
339 }
wxString m_FinishType
The name of external copper finish.
bool m_EdgePlating
True if the edge board is plated.
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTO...
bool m_CastellatedPads
True if castellated pads exist.
bool m_HasDielectricConstrains
True if some layers have impedance controlled tracks or have specific constrains for micro-wave appli...
std::vector< BOARD_STACKUP_ITEM * > m_list
bool m_HasThicknessConstrains
True if some layers (copper and/or dielectric) have specific thickness.
this class manage one layer needed to make a physical board it can be a solder mask,...
void Add(BOARD_STACKUP_ITEM *aItem)
Add a new item in stackup layer.

References Add(), m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, m_HasThicknessConstrains, and m_list.

◆ ~BOARD_STACKUP()

BOARD_STACKUP::~BOARD_STACKUP ( )
inline

Definition at line 249 of file class_board_stackup.h.

249 { RemoveAll(); }
void RemoveAll()
Delete all items in list and clear the list.

References RemoveAll().

Member Function Documentation

◆ Add()

void BOARD_STACKUP::Add ( BOARD_STACKUP_ITEM aItem)
inline

Add a new item in stackup layer.

Definition at line 276 of file class_board_stackup.h.

276 { m_list.push_back( aItem ); }
std::vector< BOARD_STACKUP_ITEM * > m_list

References m_list.

Referenced by BOARD_STACKUP(), BuildDefaultStackupList(), CADSTAR_PCB_ARCHIVE_LOADER::loadBoardStackup(), operator=(), PCB_PARSER::parseBoardStackup(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

◆ BuildBoardTicknessFromStackup()

int BOARD_STACKUP::BuildBoardTicknessFromStackup ( ) const
Returns
the board thickness ( in UI) from the thickness of BOARD_STACKUP_ITEM list

Definition at line 383 of file class_board_stackup.cpp.

384 {
385  // return the board thickness from the thickness of BOARD_STACKUP_ITEM list
386  int thickness = 0;
387 
388  for( auto item : m_list )
389  {
390  if( item->IsThicknessEditable() && item->IsEnabled() )
391  thickness += item->GetThickness();
392  }
393 
394  return thickness;
395 }
std::vector< BOARD_STACKUP_ITEM * > m_list

References m_list.

◆ BuildDefaultStackupList()

void BOARD_STACKUP::BuildDefaultStackupList ( BOARD_DESIGN_SETTINGS aSettings,
int  aActiveCopperLayersCount = 0 
)

Creates a default stackup, according to the current BOARD_DESIGN_SETTINGS settings.

Parameters
aSettingsis the current board setting. if nullptr, build a full stackup (with 32 copper layers)
aActiveCopperLayersCountis used only if aSettings == nullptr is the number of copper layers to use to calculate a default dielectric thickness. ((<= 0 to use all copper layers)

Definition at line 491 of file class_board_stackup.cpp.

493 {
494  // Creates a default stackup, according to the current BOARD_DESIGN_SETTINGS settings.
495  // Note: the m_TypeName string is made translatable using _HKI marker, but is not
496  // translated when building the stackup.
497  // It will be used as this in files, and can be translated only in dialog
498  // if aSettings == NULL, build a full stackup (with 32 copper layers)
499  LSET enabledLayer = aSettings ? aSettings->GetEnabledLayers() : StackupAllowedBrdLayers();
500  int copperLayerCount = aSettings ? aSettings->GetCopperLayerCount() : B_Cu+1;
501 
502  // We need to calculate a suitable dielectric layer thickness.
503  // If no settings, and if aActiveCopperLayersCount is given, use it
504  // (If no settings, and no aActiveCopperLayersCount, the full 32 layers are used)
505  int activeCuLayerCount = copperLayerCount;
506 
507  if( aSettings == nullptr && aActiveCopperLayersCount > 0 )
508  activeCuLayerCount = aActiveCopperLayersCount;
509 
510  int brd__thickness = aSettings ? aSettings->GetBoardThickness() : Millimeter2iu( 1.6 );
511  int diel_thickness = brd__thickness -
512  ( BOARD_STACKUP_ITEM::GetCopperDefaultThickness() * activeCuLayerCount );
513 
514  // Take in account the solder mask thickness:
515  int sm_count = ( enabledLayer & LSET( 2, F_Mask, B_Mask) ).count();
516  diel_thickness -= BOARD_STACKUP_ITEM::GetMaskDefaultThickness() * sm_count;
517 
518  int dielectric_idx = 0;
519 
520  // Add silk screen, solder mask and solder paste layers on top
521  if( enabledLayer[F_SilkS] )
522  {
524  item->SetBrdLayerId( F_SilkS );
525  item->SetTypeName( _HKI( "Top Silk Screen" ) );
526  Add( item );
527  }
528 
529  if( enabledLayer[F_Paste] )
530  {
532  item->SetBrdLayerId( F_Paste );
533  item->SetTypeName( _HKI( "Top Solder Paste" ) );
534  Add( item );
535  }
536 
537  if( enabledLayer[F_Mask] )
538  {
540  item->SetBrdLayerId( F_Mask );
541  item->SetTypeName( _HKI( "Top Solder Mask" ) );
542  Add( item );
543  }
544 
545  // Add copper and dielectric layers
546  for( int ii = 0; ii < copperLayerCount; ii++ )
547  {
549  item->SetBrdLayerId( ( PCB_LAYER_ID )ii );
550  item->SetTypeName( KEY_COPPER );
551  Add( item );
552 
553  if( ii == copperLayerCount-1 )
554  {
555  item->SetBrdLayerId( B_Cu );
556  break;
557  }
558 
559  // Add the dielectric layer:
561  item->SetThickness( diel_thickness );
562  item->SetDielectricLayerId( dielectric_idx + 1 );
563 
564  // Display a dielectric default layer name:
565  if( (dielectric_idx & 1) == 0 )
566  {
567  item->SetTypeName( KEY_CORE );
568  item->SetMaterial( "FR4" );
569  }
570  else
571  {
572  item->SetTypeName( KEY_PREPREG );
573  item->SetMaterial( "FR4" );
574  }
575 
576  Add( item );
577  dielectric_idx++;
578  }
579 
580  // Add silk screen, solder mask and solder paste layers on bottom
581  if( enabledLayer[B_Mask] )
582  {
584  item->SetBrdLayerId( B_Mask );
585  item->SetTypeName( _HKI( "Bottom Solder Mask" ) );
586  Add( item );
587  }
588 
589  if( enabledLayer[B_Paste] )
590  {
592  item->SetBrdLayerId( B_Paste );
593  item->SetTypeName( _HKI( "Bottom Solder Paste" ) );
594  Add( item );
595  }
596 
597  if( enabledLayer[B_SilkS] )
598  {
600  item->SetBrdLayerId( B_SilkS );
601  item->SetTypeName( _HKI( "Bottom Silk Screen" ) );
602  Add( item );
603  }
604 
605  // Transfer other stackup settings from aSettings
606  if( aSettings )
607  {
608  BOARD_STACKUP& source_stackup = aSettings->GetStackupDescriptor();
611  m_CastellatedPads = source_stackup.m_CastellatedPads;
612  m_EdgePlating = source_stackup.m_EdgePlating;
613  m_FinishType = source_stackup.m_FinishType;
614  }
615 }
void SetBrdLayerId(PCB_LAYER_ID aBrdLayerId)
void SetTypeName(const wxString &aName)
this class manage the layers needed to make a physical board they are solder mask,...
wxString m_FinishType
The name of external copper finish.
bool m_EdgePlating
True if the edge board is plated.
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTO...
bool m_CastellatedPads
True if castellated pads exist.
#define KEY_COPPER
static int GetCopperDefaultThickness()
bool m_HasDielectricConstrains
True if some layers have impedance controlled tracks or have specific constrains for micro-wave appli...
BOARD_STACKUP & GetStackupDescriptor()
PCB_LAYER_ID
A quick note on layer IDs:
LSET is a set of PCB_LAYER_IDs.
static LSET StackupAllowedBrdLayers()
void SetDielectricLayerId(int aLayerId)
void SetMaterial(const wxString &aName, int aDielectricSubLayer=0)
#define KEY_PREPREG
this class manage one layer needed to make a physical board it can be a solder mask,...
void SetThickness(int aThickness, int aDielectricSubLayer=0)
static int GetMaskDefaultThickness()
LSET GetEnabledLayers() const
Function GetEnabledLayers returns a bit-mask of all the layers that are enabled.
#define KEY_CORE
void Add(BOARD_STACKUP_ITEM *aItem)
Add a new item in stackup layer.
static constexpr int Millimeter2iu(double mm)
#define _HKI(x)
int GetCopperLayerCount() const
Function GetCopperLayerCount.

References _HKI, Add(), B_Cu, B_Mask, B_Paste, B_SilkS, BS_ITEM_TYPE_COPPER, BS_ITEM_TYPE_DIELECTRIC, BS_ITEM_TYPE_SILKSCREEN, BS_ITEM_TYPE_SOLDERMASK, BS_ITEM_TYPE_SOLDERPASTE, F_Mask, F_Paste, F_SilkS, BOARD_DESIGN_SETTINGS::GetBoardThickness(), BOARD_STACKUP_ITEM::GetCopperDefaultThickness(), BOARD_DESIGN_SETTINGS::GetCopperLayerCount(), BOARD_DESIGN_SETTINGS::GetEnabledLayers(), BOARD_STACKUP_ITEM::GetMaskDefaultThickness(), BOARD_DESIGN_SETTINGS::GetStackupDescriptor(), KEY_COPPER, KEY_CORE, KEY_PREPREG, m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, Millimeter2iu(), BOARD_STACKUP_ITEM::SetBrdLayerId(), BOARD_STACKUP_ITEM::SetDielectricLayerId(), BOARD_STACKUP_ITEM::SetMaterial(), BOARD_STACKUP_ITEM::SetThickness(), BOARD_STACKUP_ITEM::SetTypeName(), and StackupAllowedBrdLayers().

Referenced by PANEL_SETUP_BOARD_STACKUP::buildLayerStackPanel(), ALTIUM_PCB::ParseBoard6Data(), and SynchronizeWithBoard().

◆ FormatBoardStackup()

void BOARD_STACKUP::FormatBoardStackup ( OUTPUTFORMATTER aFormatter,
BOARD aBoard,
int  aNestLevel 
) const

Writes the stackup info on board file.

Parameters
aFormatteris the OUTPUTFORMATTER used to create the file
aBoardis the board
aNestLevelis the index to nest level to indent the lines in file

Definition at line 618 of file class_board_stackup.cpp.

620 {
621  // Board stackup is the ordered list from top to bottom of
622  // physical layers and substrate used to build the board.
623  if( m_list.empty() )
624  return;
625 
626  aFormatter->Print( aNestLevel, "(stackup\n" );
627  int nest_level = aNestLevel+1;
628 
629  // Note:
630  // Unspecified parameters are not stored in file.
631  for( BOARD_STACKUP_ITEM* item: m_list )
632  {
633  wxString layer_name;
634 
635  if( item->GetBrdLayerId() == UNDEFINED_LAYER )
636  layer_name.Printf( "dielectric %d", item->GetDielectricLayerId() );
637  else
638  layer_name = LSET::Name( item->GetBrdLayerId() );
639 
640  aFormatter->Print( nest_level, "(layer %s (type %s)",
641  aFormatter->Quotew( layer_name ).c_str(),
642  aFormatter->Quotew( item->GetTypeName() ).c_str() );
643 
644  if( item->IsColorEditable() && IsPrmSpecified( item->GetColor() ) )
645  aFormatter->Print( 0, " (color %s)",
646  aFormatter->Quotew( item->GetColor() ).c_str() );
647 
648  for( int idx = 0; idx < item->GetSublayersCount(); idx++ )
649  {
650  if( idx ) // not for the main (first) layer.
651  {
652  aFormatter->Print( 0, "\n" );
653  aFormatter->Print( nest_level+1, "addsublayer" );
654  }
655 
656  if( item->IsThicknessEditable() )
657  {
658  if( item->GetType() == BS_ITEM_TYPE_DIELECTRIC && item->IsThicknessLocked( idx ) )
659  aFormatter->Print( 0, " (thickness %s locked)",
660  FormatInternalUnits( item->GetThickness( idx ) ).c_str() );
661  else
662  aFormatter->Print( 0, " (thickness %s)",
663  FormatInternalUnits( item->GetThickness( idx ) ).c_str() );
664  }
665 
666  if( item->HasMaterialValue( idx ) )
667  aFormatter->Print( 0, " (material %s)",
668  aFormatter->Quotew( item->GetMaterial( idx ) ).c_str() );
669 
670  if( item->HasEpsilonRValue() && item->HasMaterialValue( idx ) )
671  aFormatter->Print( 0, " (epsilon_r %g)", item->GetEpsilonR( idx ) );
672 
673  if( item->HasLossTangentValue() && item->HasMaterialValue( idx ) )
674  aFormatter->Print( 0, " (loss_tangent %s)",
675  Double2Str(item->GetLossTangent( idx ) ).c_str() );
676  }
677 
678  aFormatter->Print( 0, ")\n" );
679  }
680 
681  // Other infos about board, related to layers and other fabrication specifications
683  aFormatter->Print( nest_level, "(copper_finish %s)\n",
684  aFormatter->Quotew( m_FinishType ).c_str() );
685 
686  aFormatter->Print( nest_level, "(dielectric_constraints %s)\n",
687  m_HasDielectricConstrains ? "yes" : "no" );
688 
690  aFormatter->Print( nest_level, "(edge_connector %s)\n",
691  m_EdgeConnectorConstraints > 1 ? "bevelled": "yes" );
692 
693  if( m_CastellatedPads )
694  aFormatter->Print( nest_level, "(castellated_pads yes)\n" );
695 
696  if( m_EdgePlating )
697  aFormatter->Print( nest_level, "(edge_plating yes)\n" );
698 
699  aFormatter->Print( aNestLevel, ")\n" );
700 }
wxString m_FinishType
The name of external copper finish.
bool m_EdgePlating
True if the edge board is plated.
bool IsPrmSpecified(const wxString &aPrmValue)
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTO...
bool m_CastellatedPads
True if castellated pads exist.
std::string Double2Str(double aValue)
Helper function Double2Str to print a float number without using scientific notation and no trailing ...
Definition: base_units.cpp:61
bool m_HasDielectricConstrains
True if some layers have impedance controlled tracks or have specific constrains for micro-wave appli...
static const wxChar * Name(PCB_LAYER_ID aLayerId)
Return the fixed name association with aLayerId.
Definition: lset.cpp:81
std::string Quotew(const wxString &aWrapee)
Definition: richio.cpp:476
std::vector< BOARD_STACKUP_ITEM * > m_list
this class manage one layer needed to make a physical board it can be a solder mask,...
int PRINTF_FUNC Print(int nestLevel, const char *fmt,...)
Function Print formats and writes text to the output stream.
Definition: richio.cpp:408
std::string FormatInternalUnits(int aValue)
Function FormatInternalUnits converts aValue from internal units to a string appropriate for writing ...
Definition: base_units.cpp:528

References BS_ITEM_TYPE_DIELECTRIC, Double2Str(), FormatInternalUnits(), IsPrmSpecified(), m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, m_list, LSET::Name(), OUTPUTFORMATTER::Print(), OUTPUTFORMATTER::Quotew(), and UNDEFINED_LAYER.

Referenced by PCB_IO::formatSetup(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

◆ GetCount()

int BOARD_STACKUP::GetCount ( )
inline
Returns
the number of layers in the stackup

Definition at line 270 of file class_board_stackup.h.

270 { return (int) m_list.size(); }
std::vector< BOARD_STACKUP_ITEM * > m_list

References m_list.

Referenced by GERBER_JOBFILE_WRITER::addJSONMaterialStackup(), and GetStackupLayer().

◆ GetList()

◆ GetStackupLayer()

BOARD_STACKUP_ITEM * BOARD_STACKUP::GetStackupLayer ( int  aIndex)
Returns
a reference to the layer aIndex, or nullptr if not exists

Definition at line 374 of file class_board_stackup.cpp.

375 {
376  if( aIndex < 0 || aIndex >= GetCount() )
377  return nullptr;
378 
379  return GetList()[aIndex];
380 }
std::vector< BOARD_STACKUP_ITEM * > & GetList()

References GetCount(), and GetList().

Referenced by GERBER_JOBFILE_WRITER::addJSONMaterialStackup(), and CADSTAR_PCB_ARCHIVE_LOADER::loadBoardStackup().

◆ operator=()

BOARD_STACKUP & BOARD_STACKUP::operator= ( const BOARD_STACKUP aOther)

Definition at line 342 of file class_board_stackup.cpp.

343 {
348  m_EdgePlating = aOther.m_EdgePlating;
349  m_FinishType = aOther.m_FinishType;
350 
351  RemoveAll();
352 
353  // All items in aOther.m_list have to be duplicated, because aOther.m_list
354  // manage pointers to these items
355  for( auto item : aOther.m_list )
356  {
357  BOARD_STACKUP_ITEM* dup_item = new BOARD_STACKUP_ITEM( *item );
358  Add( dup_item );
359  }
360 
361  return *this;
362 }
wxString m_FinishType
The name of external copper finish.
bool m_EdgePlating
True if the edge board is plated.
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTO...
bool m_CastellatedPads
True if castellated pads exist.
bool m_HasDielectricConstrains
True if some layers have impedance controlled tracks or have specific constrains for micro-wave appli...
std::vector< BOARD_STACKUP_ITEM * > m_list
bool m_HasThicknessConstrains
True if some layers (copper and/or dielectric) have specific thickness.
this class manage one layer needed to make a physical board it can be a solder mask,...
void RemoveAll()
Delete all items in list and clear the list.
void Add(BOARD_STACKUP_ITEM *aItem)
Add a new item in stackup layer.

References Add(), m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, m_HasThicknessConstrains, m_list, and RemoveAll().

◆ RemoveAll()

void BOARD_STACKUP::RemoveAll ( )

Delete all items in list and clear the list.

Definition at line 365 of file class_board_stackup.cpp.

366 {
367  for( auto item : m_list )
368  delete item;
369 
370  m_list.clear();
371 }
std::vector< BOARD_STACKUP_ITEM * > m_list

References m_list.

Referenced by CADSTAR_PCB_ARCHIVE_LOADER::loadBoardStackup(), operator=(), ALTIUM_PCB::ParseBoard6Data(), PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow(), and ~BOARD_STACKUP().

◆ StackupAllowedBrdLayers()

static LSET BOARD_STACKUP::StackupAllowedBrdLayers ( )
inlinestatic
Returns
the board layers full mask allowed in the stackup list i.e. the SilkS, Mask, Paste and all copper layers

Definition at line 259 of file class_board_stackup.h.

260  {
261  return LSET( 6, F_SilkS, F_Mask, F_Paste, B_SilkS, B_Mask, B_Paste )
263  }
LSET is a set of PCB_LAYER_IDs.
static LSET InternalCuMask()
Return a complete set of internal copper layers which is all Cu layers except F_Cu and B_Cu.
Definition: lset.cpp:709
static LSET ExternalCuMask()
Return a mask holding the Front and Bottom layers.
Definition: lset.cpp:779

References B_Mask, B_Paste, B_SilkS, LSET::ExternalCuMask(), F_Mask, F_Paste, F_SilkS, and LSET::InternalCuMask().

Referenced by BuildDefaultStackupList(), PANEL_SETUP_BOARD_STACKUP::ImportSettingsFrom(), PANEL_SETUP_BOARD_STACKUP::OnLayersOptionsChanged(), PANEL_SETUP_BOARD_STACKUP::PANEL_SETUP_BOARD_STACKUP(), and PANEL_SETUP_BOARD_STACKUP::transferDataFromUIToStackup().

◆ SynchronizeWithBoard()

bool BOARD_STACKUP::SynchronizeWithBoard ( BOARD_DESIGN_SETTINGS aSettings)

Synchronize the BOARD_STACKUP_ITEM* list with the board.

Not enabled layers are removed Missing layers are added

Parameters
aSettings,isthe current board setting.
Returns
true if changes are made

Definition at line 398 of file class_board_stackup.cpp.

399 {
400  bool change = false;
401  // Build the suitable stackup:
402  BOARD_STACKUP stackup;
403  stackup.BuildDefaultStackupList( aSettings );
404 
405  // First, find removed layers:
406  for( BOARD_STACKUP_ITEM* curr_item: m_list )
407  {
408  bool found = false;
409 
410  for( BOARD_STACKUP_ITEM* item: stackup.GetList() )
411  {
412  if( curr_item->GetBrdLayerId() != UNDEFINED_LAYER )
413  {
414  if( item->GetBrdLayerId() == curr_item->GetBrdLayerId() )
415  {
416  found = true;
417  break;
418  }
419  }
420  else // curr_item = dielectric layer
421  {
422  if( item->GetBrdLayerId() != UNDEFINED_LAYER )
423  continue;
424 
425  if( item->GetDielectricLayerId() == curr_item->GetDielectricLayerId() )
426  {
427  found = true;
428  break;
429  }
430  }
431  }
432 
433  if( !found ) // a layer was removed: a change is found
434  {
435  change = true;
436  break;
437  }
438  }
439 
440  // Now initialize all stackup items to the initial values, when exist
441  for( BOARD_STACKUP_ITEM* item: stackup.GetList() )
442  {
443  bool found = false;
444  // Search for initial settings:
445  for( BOARD_STACKUP_ITEM* initial_item: m_list )
446  {
447  if( item->GetBrdLayerId() != UNDEFINED_LAYER )
448  {
449  if( item->GetBrdLayerId() == initial_item->GetBrdLayerId() )
450  {
451  *item = *initial_item;
452  found = true;
453  break;
454  }
455  }
456  else // dielectric layer: see m_DielectricLayerId for identification
457  {
458  // Compare dielectric layer with dielectric layer
459  if( initial_item->GetBrdLayerId() != UNDEFINED_LAYER )
460  continue;
461 
462  if( item->GetDielectricLayerId() == initial_item->GetDielectricLayerId() )
463  {
464  *item = *initial_item;
465  found = true;
466  break;
467  }
468  }
469  }
470 
471  if( !found )
472  {
473  change = true;
474  }
475  }
476 
477  // Transfer other stackup settings from aSettings
478  BOARD_STACKUP& source_stackup = aSettings->GetStackupDescriptor();
481  m_CastellatedPads = source_stackup.m_CastellatedPads;
482  m_EdgePlating = source_stackup.m_EdgePlating;
483  m_FinishType = source_stackup.m_FinishType;
484 
485  *this = stackup;
486 
487  return change;
488 }
std::vector< BOARD_STACKUP_ITEM * > & GetList()
this class manage the layers needed to make a physical board they are solder mask,...
wxString m_FinishType
The name of external copper finish.
bool m_EdgePlating
True if the edge board is plated.
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints
If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTO...
bool m_CastellatedPads
True if castellated pads exist.
bool m_HasDielectricConstrains
True if some layers have impedance controlled tracks or have specific constrains for micro-wave appli...
BOARD_STACKUP & GetStackupDescriptor()
std::vector< BOARD_STACKUP_ITEM * > m_list
this class manage one layer needed to make a physical board it can be a solder mask,...
void BuildDefaultStackupList(BOARD_DESIGN_SETTINGS *aSettings, int aActiveCopperLayersCount=0)
Creates a default stackup, according to the current BOARD_DESIGN_SETTINGS settings.

References BuildDefaultStackupList(), GetList(), BOARD_DESIGN_SETTINGS::GetStackupDescriptor(), m_CastellatedPads, m_EdgeConnectorConstraints, m_EdgePlating, m_FinishType, m_HasDielectricConstrains, m_list, and UNDEFINED_LAYER.

Referenced by GERBER_JOBFILE_WRITER::addJSONMaterialStackup().

Member Data Documentation

◆ m_CastellatedPads

◆ m_EdgeConnectorConstraints

BS_EDGE_CONNECTOR_CONSTRAINTS BOARD_STACKUP::m_EdgeConnectorConstraints

If the board has edge connector cards, some constrains can be specified in job file: BS_EDGE_CONNECTOR_NONE = no edge connector BS_EDGE_CONNECTOR_IN_USE = board has edge connectors BS_EDGE_CONNECTOR_BEVELLED = edge connectors are beveled.

Definition at line 239 of file class_board_stackup.h.

Referenced by BOARD_STACKUP(), BuildDefaultStackupList(), BuildStackupReport(), FormatBoardStackup(), operator=(), PCB_PARSER::parseBoardStackup(), PANEL_SETUP_BOARD_STACKUP::synchronizeWithBoard(), SynchronizeWithBoard(), PANEL_SETUP_BOARD_STACKUP::transferDataFromUIToStackup(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

◆ m_EdgePlating

◆ m_FinishType

◆ m_HasDielectricConstrains

bool BOARD_STACKUP::m_HasDielectricConstrains

True if some layers have impedance controlled tracks or have specific constrains for micro-wave applications If the board has dielectric constrains, the .gbrjob will contain info about dielectric constrains: loss tangent and Epsilon rel.

If not, these values will be not specified in job file.

Definition at line 227 of file class_board_stackup.h.

Referenced by GERBER_JOBFILE_WRITER::addJSONMaterialStackup(), BOARD_STACKUP(), BuildDefaultStackupList(), BuildStackupReport(), FormatBoardStackup(), operator=(), PCB_PARSER::parseBoardStackup(), PANEL_SETUP_BOARD_STACKUP::synchronizeWithBoard(), SynchronizeWithBoard(), PANEL_SETUP_BOARD_STACKUP::transferDataFromUIToStackup(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

◆ m_HasThicknessConstrains

bool BOARD_STACKUP::m_HasThicknessConstrains

True if some layers (copper and/or dielectric) have specific thickness.

Definition at line 231 of file class_board_stackup.h.

Referenced by BOARD_STACKUP(), and operator=().

◆ m_list


The documentation for this class was generated from the following files: