KiCad PCB EDA Suite
BOARD_DESIGN_SETTINGS Class Reference

BOARD_DESIGN_SETTINGS contains design settings for a BOARD object. More...

#include <board_design_settings.h>

Public Member Functions

 BOARD_DESIGN_SETTINGS ()
 
BOARD_STACKUPGetStackupDescriptor ()
 
int GetSeverity (int aDRCErrorCode)
 
bool Ignore (int aDRCErrorCode)
 returns true if the DRC error code's severity is SEVERITY_IGNORE More...
 
NETCLASSPTR GetDefault () const
 Function GetDefault. More...
 
const wxString & GetCurrentNetClassName () const
 Function GetCurrentNetClassName. More...
 
bool UseNetClassTrack () const
 Function UseNetClassTrack returns true if netclass values should be used to obtain appropriate track width. More...
 
bool UseNetClassVia () const
 Function UseNetClassVia returns true if netclass values should be used to obtain appropriate via size. More...
 
bool UseNetClassDiffPair () const
 Function UseNetClassDiffPair returns true if netclass values should be used to obtain appropriate diff pair dimensions. More...
 
bool SetCurrentNetClass (const wxString &aNetClassName)
 Function SetCurrentNetClass Must be called after a netclass selection (or after a netclass parameter change Initialize vias and tracks values displayed in comb boxes of the auxiliary toolbar and some others parameters (netclass name ....) More...
 
int GetBiggestClearanceValue ()
 Function GetBiggestClearanceValue. More...
 
int GetSmallestClearanceValue ()
 Function GetSmallestClearanceValue. More...
 
int GetCurrentMicroViaSize ()
 Function GetCurrentMicroViaSize. More...
 
int GetCurrentMicroViaDrill ()
 Function GetCurrentMicroViaDrill. More...
 
unsigned GetTrackWidthIndex () const
 Function GetTrackWidthIndex. More...
 
void SetTrackWidthIndex (unsigned aIndex)
 Function SetTrackWidthIndex sets the current track width list index to aIndex. More...
 
int GetCurrentTrackWidth () const
 Function GetCurrentTrackWidth. More...
 
void SetCustomTrackWidth (int aWidth)
 Function SetCustomTrackWidth Sets custom width for track (i.e. More...
 
int GetCustomTrackWidth () const
 Function GetCustomTrackWidth. More...
 
unsigned GetViaSizeIndex () const
 Function GetViaSizeIndex. More...
 
void SetViaSizeIndex (unsigned aIndex)
 Function SetViaSizeIndex sets the current via size list index to aIndex. More...
 
int GetCurrentViaSize () const
 Function GetCurrentViaSize. More...
 
void SetCustomViaSize (int aSize)
 Function SetCustomViaSize Sets custom size for via diameter (i.e. More...
 
int GetCustomViaSize () const
 Function GetCustomViaSize. More...
 
int GetCurrentViaDrill () const
 Function GetCurrentViaDrill. More...
 
void SetCustomViaDrill (int aDrill)
 Function SetCustomViaDrill Sets custom size for via drill (i.e. More...
 
int GetCustomViaDrill () const
 Function GetCustomViaDrill. More...
 
void UseCustomTrackViaSize (bool aEnabled)
 Function UseCustomTrackViaSize Enables/disables custom track/via size settings. More...
 
bool UseCustomTrackViaSize () const
 Function UseCustomTrackViaSize. More...
 
unsigned GetDiffPairIndex () const
 Function GetDiffPairIndex. More...
 
void SetDiffPairIndex (unsigned aIndex)
 Function SetDiffPairIndex. More...
 
void SetCustomDiffPairWidth (int aWidth)
 Function SetCustomDiffPairWidth Sets custom track width for differential pairs (i.e. More...
 
int GetCustomDiffPairWidth ()
 Function GetCustomDiffPairWidth. More...
 
void SetCustomDiffPairGap (int aGap)
 Function SetCustomDiffPairGap Sets custom gap for differential pairs (i.e. More...
 
int GetCustomDiffPairGap ()
 Function GetCustomDiffPairGap. More...
 
void SetCustomDiffPairViaGap (int aGap)
 Function SetCustomDiffPairViaGap Sets custom via gap for differential pairs (i.e. More...
 
int GetCustomDiffPairViaGap ()
 Function GetCustomDiffPairViaGap. More...
 
void UseCustomDiffPairDimensions (bool aEnabled)
 Function UseCustomDiffPairDimensions Enables/disables custom differential pair dimensions. More...
 
bool UseCustomDiffPairDimensions () const
 Function UseCustomDiffPairDimensions. More...
 
int GetCurrentDiffPairWidth () const
 Function GetCurrentDiffPairWidth. More...
 
int GetCurrentDiffPairGap () const
 Function GetCurrentDiffPairGap. More...
 
int GetCurrentDiffPairViaGap () const
 Function GetCurrentDiffPairViaGap. More...
 
void SetMinHoleSeparation (int aDistance)
 Function SetMinHoleSeparation. More...
 
void SetCopperEdgeClearance (int aDistance)
 Function SetCopperEdgeClearance. More...
 
LSET GetVisibleLayers () const
 Function GetVisibleLayers returns a bit-mask of all the layers that are visible. More...
 
void SetVisibleAlls ()
 Function SetVisibleAlls Set the bit-mask of all visible elements categories, including enabled layers. More...
 
void SetVisibleLayers (LSET aMask)
 Function SetVisibleLayers changes the bit-mask of visible layers. More...
 
bool IsLayerVisible (PCB_LAYER_ID aLayerId) const
 Function IsLayerVisible tests whether a given layer is visible. More...
 
void SetLayerVisibility (PCB_LAYER_ID aLayerId, bool aNewState)
 Function SetLayerVisibility changes the visibility of a given layer. More...
 
int GetVisibleElements () const
 Function GetVisibleElements returns a bit-mask of all the element categories that are visible. More...
 
void SetVisibleElements (int aMask)
 Function SetVisibleElements changes the bit-mask of visible element categories. More...
 
bool IsElementVisible (GAL_LAYER_ID aElementCategory) const
 Function IsElementVisible tests whether a given element category is visible. More...
 
void SetElementVisibility (GAL_LAYER_ID aElementCategory, bool aNewState)
 Function SetElementVisibility changes the visibility of an element category. More...
 
LSET GetEnabledLayers () const
 Function GetEnabledLayers returns a bit-mask of all the layers that are enabled. More...
 
void SetEnabledLayers (LSET aMask)
 Function SetEnabledLayers changes the bit-mask of enabled layers. More...
 
bool IsLayerEnabled (PCB_LAYER_ID aLayerId) const
 Function IsLayerEnabled tests whether a given layer is enabled. More...
 
int GetCopperLayerCount () const
 Function GetCopperLayerCount. More...
 
void SetCopperLayerCount (int aNewLayerCount)
 Function SetCopperLayerCount do what its name says... More...
 
void AppendConfigs (BOARD *aBoard, std::vector< PARAM_CFG * > *aResult)
 Function AppendConfigs appends to aResult the configuration setting accessors which will later allow reading or writing of configuration file information directly into this object. More...
 
int GetBoardThickness () const
 
void SetBoardThickness (int aThickness)
 
int GetLineThickness (PCB_LAYER_ID aLayer) const
 Function GetLineThickness Returns the default graphic segment thickness from the layer class for the given layer. More...
 
wxSize GetTextSize (PCB_LAYER_ID aLayer) const
 Function GetTextSize Returns the default text size from the layer class for the given layer. More...
 
int GetTextThickness (PCB_LAYER_ID aLayer) const
 Function GetTextThickness Returns the default text thickness from the layer class for the given layer. More...
 
bool GetTextItalic (PCB_LAYER_ID aLayer) const
 
bool GetTextUpright (PCB_LAYER_ID aLayer) const
 
int GetLayerClass (PCB_LAYER_ID aLayer) const
 

Public Attributes

std::vector< int > m_TrackWidthList
 
std::vector< VIA_DIMENSIONm_ViasDimensionsList
 
std::vector< DIFF_PAIR_DIMENSIONm_DiffPairDimensionsList
 
NETCLASSES m_NetClasses
 
bool m_MicroViasAllowed
 true to allow micro vias More...
 
bool m_BlindBuriedViaAllowed
 true to allow blind/buried vias More...
 
VIATYPE m_CurrentViaType
 (VIA_BLIND_BURIED, VIA_THROUGH, VIA_MICROVIA) More...
 
bool m_UseConnectedTrackWidth
 
int m_TrackMinWidth
 
int m_ViasMinSize
 
int m_ViasMinDrill
 
int m_MicroViasMinSize
 
int m_MicroViasMinDrill
 
int m_CopperEdgeClearance
 
int m_HoleToHoleMin
 
std::map< int, int > m_DRCSeverities
 
bool m_ZoneUseNoOutlineInFill
 Option to handle filled polygons in zones: the "legacy" option is using thick outlines around filled polygons: give the best shape the "new" option is using only filled polygons (no outline: give the faster redraw time moreover when exporting zone filled areas, the excatct shape is exported. More...
 
int m_MaxError
 
int m_SolderMaskMargin
 Solder mask margin. More...
 
int m_SolderMaskMinWidth
 Solder mask min width. More...
 
int m_SolderPasteMargin
 Solder paste margin absolute value. More...
 
double m_SolderPasteMarginRatio
 Solder pask margin ratio value of pad size The final margin is the sum of these 2 values. More...
 
int m_LineThickness [LAYER_CLASS_COUNT]
 
wxSize m_TextSize [LAYER_CLASS_COUNT]
 
int m_TextThickness [LAYER_CLASS_COUNT]
 
bool m_TextItalic [LAYER_CLASS_COUNT]
 
bool m_TextUpright [LAYER_CLASS_COUNT]
 
int m_DimensionUnits
 
int m_DimensionPrecision
 
wxString m_RefDefaultText
 Default ref text on fp creation. More...
 
bool m_RefDefaultVisibility
 Default ref text visibility on fp creation. More...
 
int m_RefDefaultlayer
 Default ref text layer on fp creation. More...
 
wxString m_ValueDefaultText
 Default value text on fp creation. More...
 
bool m_ValueDefaultVisibility
 Default value text visibility on fp creation. More...
 
int m_ValueDefaultlayer
 Default value text layer on fp creation. More...
 
wxPoint m_AuxOrigin
 origin for plot exports More...
 
wxPoint m_GridOrigin
 origin for grid offsets More...
 
D_PAD m_Pad_Master
 A dummy pad to store all default parameters. More...
 
bool m_HasStackup
 Set to true if the board has a stackup management. More...
 

Private Member Functions

void formatNetClass (NETCLASS *aNetClass, OUTPUTFORMATTER *aFormatter, int aNestLevel, int aControlBits) const
 

Private Attributes

unsigned m_trackWidthIndex
 
unsigned m_viaSizeIndex
 
unsigned m_diffPairIndex
 
bool m_useCustomTrackVia
 
int m_customTrackWidth
 
VIA_DIMENSION m_customViaSize
 
bool m_useCustomDiffPair
 
DIFF_PAIR_DIMENSION m_customDiffPair
 
int m_copperLayerCount
 Number of copper layers for this design. More...
 
LSET m_enabledLayers
 Bit-mask for layer enabling. More...
 
LSET m_visibleLayers
 Bit-mask for layer visibility. More...
 
int m_visibleElements
 Bit-mask for element category visibility. More...
 
int m_boardThickness
 Board thickness for 3D viewer. More...
 
wxString m_currentNetClassName
 Current net class name used to display netclass info. More...
 
BOARD_STACKUP m_stackup
 the description of layers stackup, for board fabrication only physical layers are in layers stackup. More...
 

Detailed Description

BOARD_DESIGN_SETTINGS contains design settings for a BOARD object.

Definition at line 183 of file board_design_settings.h.

Constructor & Destructor Documentation

◆ BOARD_DESIGN_SETTINGS()

BOARD_DESIGN_SETTINGS::BOARD_DESIGN_SETTINGS ( )

Definition at line 493 of file board_design_settings.cpp.

493  :
494  m_Pad_Master( NULL )
495 {
496  m_HasStackup = false; // no stackup defined by default
497 
498  LSET all_set = LSET().set();
499  m_enabledLayers = all_set; // All layers enabled at first.
500  // SetCopperLayerCount() will adjust this.
501  SetVisibleLayers( all_set );
502 
503  // set all but hidden text as visible.
505 
506  SetCopperLayerCount( 2 ); // Default design is a double sided board
508 
509  // if true, when creating a new track starting on an existing track, use this track width
510  m_UseConnectedTrackWidth = false;
511 
512  m_BlindBuriedViaAllowed = false;
513  m_MicroViasAllowed = false;
514 
516  m_TextSize[ LAYER_CLASS_SILK ] = wxSize( Millimeter2iu( DEFAULT_SILK_TEXT_SIZE ),
517  Millimeter2iu( DEFAULT_SILK_TEXT_SIZE ) );
519  m_TextItalic[ LAYER_CLASS_SILK ] = false;
520  m_TextUpright[ LAYER_CLASS_SILK ] = false;
521 
523  m_TextSize[ LAYER_CLASS_COPPER ] = wxSize( Millimeter2iu( DEFAULT_COPPER_TEXT_SIZE ),
524  Millimeter2iu( DEFAULT_COPPER_TEXT_SIZE ) );
526  m_TextItalic[ LAYER_CLASS_COPPER ] = false;
528 
529  // Edges & Courtyards; text properties aren't used but better to have them holding
530  // reasonable values than not.
532  m_TextSize[ LAYER_CLASS_EDGES ] = wxSize( Millimeter2iu( DEFAULT_TEXT_SIZE ),
533  Millimeter2iu( DEFAULT_TEXT_SIZE ) );
535  m_TextItalic[ LAYER_CLASS_EDGES ] = false;
536  m_TextUpright[ LAYER_CLASS_EDGES ] = false;
537 
539  m_TextSize[ LAYER_CLASS_COURTYARD ] = wxSize( Millimeter2iu( DEFAULT_TEXT_SIZE ),
540  Millimeter2iu( DEFAULT_TEXT_SIZE ) );
544 
546  m_TextSize[ LAYER_CLASS_OTHERS ] = wxSize( Millimeter2iu( DEFAULT_TEXT_SIZE ),
547  Millimeter2iu( DEFAULT_TEXT_SIZE ) );
549  m_TextItalic[ LAYER_CLASS_OTHERS ] = false;
551 
552  m_DimensionUnits = 0; // Inches
553  m_DimensionPrecision = 1; // 0.001mm / 0.1 mil
554 
555  m_useCustomTrackVia = false;
556  m_customTrackWidth = Millimeter2iu( DEFAULT_CUSTOMTRACKWIDTH );
558  m_customViaSize.m_Drill = Millimeter2iu( DEFAULT_VIASMINDRILL );
559 
560  m_useCustomDiffPair = false;
562  m_customDiffPair.m_Gap = Millimeter2iu( DEFAULT_CUSTOMDPAIRGAP );
564 
565  m_TrackMinWidth = Millimeter2iu( DEFAULT_TRACKMINWIDTH );
566  m_ViasMinSize = Millimeter2iu( DEFAULT_VIASMINSIZE );
567  m_ViasMinDrill = Millimeter2iu( DEFAULT_VIASMINDRILL );
568  m_MicroViasMinSize = Millimeter2iu( DEFAULT_MICROVIASMINSIZE );
571  m_HoleToHoleMin = Millimeter2iu( DEFAULT_HOLETOHOLEMIN );
572 
573  for( int errorCode = DRCE_FIRST; errorCode <= DRCE_LAST; ++errorCode )
574  m_DRCSeverities[ errorCode ] = RPT_SEVERITY_ERROR;
575 
577 
581 
582  m_MaxError = ARC_HIGH_DEF;
583  m_ZoneUseNoOutlineInFill = false; // Use compatibility mode by default
584 
585  // Global mask margins:
588  m_SolderPasteMargin = 0; // Solder paste margin absolute value
589  m_SolderPasteMarginRatio = 0.0; // Solder paste margin as a ratio of pad size
590  // The final margin is the sum of these 2 values
591  // Usually < 0 because the mask is smaller than pad
592  // Layer thickness for 3D viewer
593  m_boardThickness = Millimeter2iu( DEFAULT_BOARD_THICKNESS_MM );
594 
595  m_viaSizeIndex = 0;
596  m_trackWidthIndex = 0;
597  m_diffPairIndex = 0;
598 
599  // Default ref text on fp creation. If empty, use footprint name as default
600  m_RefDefaultText = "REF**";
601  m_RefDefaultVisibility = true;
602  m_RefDefaultlayer = int( F_SilkS );
603  // Default value text on fp creation. If empty, use footprint name as default
604  m_ValueDefaultText = "";
606  m_ValueDefaultlayer = int( F_Fab );
607 }
#define DEFAULT_EDGE_WIDTH
#define DEFAULT_SILK_TEXT_WIDTH
wxString m_RefDefaultText
Default ref text on fp creation.
int m_SolderMaskMargin
Solder mask margin.
void SetCopperLayerCount(int aNewLayerCount)
Function SetCopperLayerCount do what its name says...
#define DEFAULT_TRACKMINWIDTH
#define DEFAULT_COURTYARD_WIDTH
bool m_ValueDefaultVisibility
Default value text visibility on fp creation.
int m_SolderPasteMargin
Solder paste margin absolute value.
#define DEFAULT_VIASMINSIZE
footprint not found for netlist item
Definition: drc.h:90
std::map< int, int > m_DRCSeverities
more than one footprints found for netlist item
Definition: drc.h:91
#define DEFAULT_BOARD_THICKNESS_MM
#define DEFAULT_LINE_WIDTH
#define DEFAULT_COPPER_LINE_WIDTH
#define DEFAULT_HOLETOHOLEMIN
int m_ValueDefaultlayer
Default value text layer on fp creation.
DIFF_PAIR_DIMENSION m_customDiffPair
#define DEFAULT_CUSTOMDPAIRGAP
VIATYPE m_CurrentViaType
(VIA_BLIND_BURIED, VIA_THROUGH, VIA_MICROVIA)
footprint has no courtyard defined
Definition: drc.h:81
#define DEFAULT_CUSTOMDPAIRVIAGAP
void SetVisibleLayers(LSET aMask)
Function SetVisibleLayers changes the bit-mask of visible layers.
#define DEFAULT_TEXT_WIDTH
netlist item not found for footprint
Definition: drc.h:92
wxSize m_TextSize[LAYER_CLASS_COUNT]
#define DEFAULT_CUSTOMDPAIRWIDTH
#define DEFAULT_SILK_TEXT_SIZE
int m_TextThickness[LAYER_CLASS_COUNT]
LSET is a set of PCB_LAYER_IDs.
#define DEFAULT_SILK_LINE_WIDTH
#define NULL
#define GAL_LAYER_INDEX(x)
Use this macro to convert a GAL layer to a 0-indexed offset from LAYER_VIAS.
Definition: drc.h:103
bool m_TextItalic[LAYER_CLASS_COUNT]
bool m_BlindBuriedViaAllowed
true to allow blind/buried vias
#define DEFAULT_MICROVIASMINSIZE
wxString m_ValueDefaultText
Default value text on fp creation.
#define DEFAULT_MICROVIASMINDRILL
#define DEFAULT_SOLDERMASK_MIN_WIDTH
int m_LineThickness[LAYER_CLASS_COUNT]
#define DEFAULT_COPPEREDGECLEARANCE
int m_visibleElements
Bit-mask for element category visibility.
bool m_ZoneUseNoOutlineInFill
Option to handle filled polygons in zones: the "legacy" option is using thick outlines around filled ...
D_PAD m_Pad_Master
A dummy pad to store all default parameters.
int m_RefDefaultlayer
Default ref text layer on fp creation.
#define DEFAULT_COPPER_TEXT_WIDTH
#define DEFAULT_CUSTOMTRACKWIDTH
#define DEFAULT_SOLDERMASK_CLEARANCE
#define DEFAULT_COPPER_TEXT_SIZE
bool m_MicroViasAllowed
true to allow micro vias
Definition: drc.h:44
bool m_HasStackup
Set to true if the board has a stackup management.
double m_SolderPasteMarginRatio
Solder pask margin ratio value of pad size The final margin is the sum of these 2 values.
#define DEFAULT_TEXT_SIZE
LSET m_enabledLayers
Bit-mask for layer enabling.
bool m_RefDefaultVisibility
Default ref text visibility on fp creation.
#define DEFAULT_VIASMINDRILL
int m_boardThickness
Board thickness for 3D viewer.
bool m_TextUpright[LAYER_CLASS_COUNT]
int m_SolderMaskMinWidth
Solder mask min width.

References DEFAULT_BOARD_THICKNESS_MM, DEFAULT_COPPER_LINE_WIDTH, DEFAULT_COPPER_TEXT_SIZE, DEFAULT_COPPER_TEXT_WIDTH, DEFAULT_COPPEREDGECLEARANCE, DEFAULT_COURTYARD_WIDTH, DEFAULT_CUSTOMDPAIRGAP, DEFAULT_CUSTOMDPAIRVIAGAP, DEFAULT_CUSTOMDPAIRWIDTH, DEFAULT_CUSTOMTRACKWIDTH, DEFAULT_EDGE_WIDTH, DEFAULT_HOLETOHOLEMIN, DEFAULT_LINE_WIDTH, DEFAULT_MICROVIASMINDRILL, DEFAULT_MICROVIASMINSIZE, DEFAULT_SILK_LINE_WIDTH, DEFAULT_SILK_TEXT_SIZE, DEFAULT_SILK_TEXT_WIDTH, DEFAULT_SOLDERMASK_CLEARANCE, DEFAULT_SOLDERMASK_MIN_WIDTH, DEFAULT_TEXT_SIZE, DEFAULT_TEXT_WIDTH, DEFAULT_TRACKMINWIDTH, DEFAULT_VIASMINDRILL, DEFAULT_VIASMINSIZE, DRCE_DUPLICATE_FOOTPRINT, DRCE_EXTRA_FOOTPRINT, DRCE_FIRST, DRCE_LAST, DRCE_MISSING_COURTYARD_IN_FOOTPRINT, DRCE_MISSING_FOOTPRINT, F_Fab, F_SilkS, GAL_LAYER_INDEX, LAYER_CLASS_COPPER, LAYER_CLASS_COURTYARD, LAYER_CLASS_EDGES, LAYER_CLASS_OTHERS, LAYER_CLASS_SILK, LAYER_MOD_TEXT_INVISIBLE, m_BlindBuriedViaAllowed, m_boardThickness, m_CopperEdgeClearance, m_CurrentViaType, m_customDiffPair, m_customTrackWidth, m_customViaSize, VIA_DIMENSION::m_Diameter, m_diffPairIndex, m_DimensionPrecision, m_DimensionUnits, m_DRCSeverities, VIA_DIMENSION::m_Drill, m_enabledLayers, DIFF_PAIR_DIMENSION::m_Gap, m_HasStackup, m_HoleToHoleMin, m_LineThickness, m_MaxError, m_MicroViasAllowed, m_MicroViasMinDrill, m_MicroViasMinSize, m_RefDefaultlayer, m_RefDefaultText, m_RefDefaultVisibility, m_SolderMaskMargin, m_SolderMaskMinWidth, m_SolderPasteMargin, m_SolderPasteMarginRatio, m_TextItalic, m_TextSize, m_TextThickness, m_TextUpright, m_TrackMinWidth, m_trackWidthIndex, m_UseConnectedTrackWidth, m_useCustomDiffPair, m_useCustomTrackVia, m_ValueDefaultlayer, m_ValueDefaultText, m_ValueDefaultVisibility, DIFF_PAIR_DIMENSION::m_ViaGap, m_viaSizeIndex, m_ViasMinDrill, m_ViasMinSize, m_visibleElements, DIFF_PAIR_DIMENSION::m_Width, m_ZoneUseNoOutlineInFill, RPT_SEVERITY_ERROR, RPT_SEVERITY_IGNORE, RPT_SEVERITY_WARNING, SetCopperLayerCount(), SetVisibleLayers(), and THROUGH.

Member Function Documentation

◆ AppendConfigs()

void BOARD_DESIGN_SETTINGS::AppendConfigs ( BOARD aBoard,
std::vector< PARAM_CFG * > *  aResult 
)

Function AppendConfigs appends to aResult the configuration setting accessors which will later allow reading or writing of configuration file information directly into this object.

Definition at line 611 of file board_design_settings.cpp.

612 {
613  aResult->push_back( new PARAM_CFG_LAYERS( aBoard ) );
614 
615  aResult->push_back( new PARAM_CFG_BOOL( wxT( "AllowMicroVias" ),
616  &m_MicroViasAllowed, false ) );
617 
618  aResult->push_back( new PARAM_CFG_BOOL( wxT( "AllowBlindVias" ),
619  &m_BlindBuriedViaAllowed, false ) );
620 
621  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "MinTrackWidth" ),
623  Millimeter2iu( DEFAULT_TRACKMINWIDTH ), Millimeter2iu( 0.01 ), Millimeter2iu( 25.0 ),
624  nullptr, MM_PER_IU ) );
625 
626  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "MinViaDiameter" ),
627  &m_ViasMinSize,
628  Millimeter2iu( DEFAULT_VIASMINSIZE ), Millimeter2iu( 0.01 ), Millimeter2iu( 25.0 ),
629  nullptr, MM_PER_IU ) );
630 
631  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "MinViaDrill" ),
633  Millimeter2iu( DEFAULT_VIASMINDRILL ), Millimeter2iu( 0.01 ), Millimeter2iu( 25.0 ),
634  nullptr, MM_PER_IU ) );
635 
636  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "MinMicroViaDiameter" ),
638  Millimeter2iu( DEFAULT_MICROVIASMINSIZE ), Millimeter2iu( 0.01 ), Millimeter2iu( 10.0 ),
639  nullptr, MM_PER_IU ) );
640 
641  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "MinMicroViaDrill" ),
643  Millimeter2iu( DEFAULT_MICROVIASMINDRILL ), Millimeter2iu( 0.01 ), Millimeter2iu( 10.0 ),
644  nullptr, MM_PER_IU ) );
645 
646  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "MinHoleToHole" ),
648  Millimeter2iu( DEFAULT_HOLETOHOLEMIN ), Millimeter2iu( 0.0 ), Millimeter2iu( 10.0 ),
649  nullptr, MM_PER_IU ) );
650 
651  aResult->push_back( new PARAM_CFG_SEVERITIES( aBoard ) );
652 
653  // Note: a clearance of -0.01 is a flag indicating we should use the legacy (pre-6.0) method
654  // based on the edge cut thicknesses.
655  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "CopperEdgeClearance" ),
657  Millimeter2iu( LEGACY_COPPEREDGECLEARANCE ), Millimeter2iu( -0.01 ), Millimeter2iu( 25.0 ),
658  nullptr, MM_PER_IU ) );
659 
660  aResult->push_back( new PARAM_CFG_TRACKWIDTHS( &m_TrackWidthList ) );
661  aResult->push_back( new PARAM_CFG_VIADIMENSIONS( &m_ViasDimensionsList ) );
662  aResult->push_back( new PARAM_CFG_DIFFPAIRDIMENSIONS( &m_DiffPairDimensionsList ) );
663 
664  aResult->push_back( new PARAM_CFG_NETCLASSES( wxT( "Netclasses" ), &m_NetClasses ) );
665 
666  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "SilkLineWidth" ),
668  Millimeter2iu( DEFAULT_SILK_LINE_WIDTH ), Millimeter2iu( 0.01 ), Millimeter2iu( 5.0 ),
669  nullptr, MM_PER_IU, wxT( "ModuleOutlineThickness" ) ) );
670 
671  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "SilkTextSizeV" ),
674  nullptr, MM_PER_IU, wxT( "ModuleTextSizeV" ) ) );
675 
676  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "SilkTextSizeH" ),
679  nullptr, MM_PER_IU, wxT( "ModuleTextSizeH" ) ) );
680 
681  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "SilkTextSizeThickness" ),
683  Millimeter2iu( DEFAULT_SILK_TEXT_WIDTH ), 1, TEXTS_MAX_WIDTH,
684  nullptr, MM_PER_IU, wxT( "ModuleTextSizeThickness" ) ) );
685 
686  aResult->push_back( new PARAM_CFG_BOOL( wxT( "SilkTextItalic" ),
687  &m_TextItalic[ LAYER_CLASS_SILK ], false ) );
688 
689  aResult->push_back( new PARAM_CFG_BOOL( wxT( "SilkTextUpright" ),
690  &m_TextUpright[ LAYER_CLASS_SILK ], true ) );
691 
692  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "CopperLineWidth" ),
694  Millimeter2iu( DEFAULT_SILK_LINE_WIDTH ), Millimeter2iu( 0.01 ), Millimeter2iu( 5.0 ),
695  nullptr, MM_PER_IU, wxT( "DrawSegmentWidth" ) ) );
696 
697  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "CopperTextSizeV" ),
700  nullptr, MM_PER_IU, wxT( "PcbTextSizeV" ) ) );
701 
702  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "CopperTextSizeH" ),
705  nullptr, MM_PER_IU, wxT( "PcbTextSizeH" ) ) );
706 
707  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "CopperTextThickness" ),
709  Millimeter2iu( DEFAULT_COPPER_TEXT_WIDTH ), Millimeter2iu( 0.01 ), Millimeter2iu( 5.0 ),
710  nullptr, MM_PER_IU, wxT( "PcbTextThickness" ) ) );
711 
712  aResult->push_back( new PARAM_CFG_BOOL( wxT( "CopperTextItalic" ),
713  &m_TextItalic[ LAYER_CLASS_COPPER ], false ) );
714 
715  aResult->push_back( new PARAM_CFG_BOOL( wxT( "CopperTextUpright" ),
716  &m_TextUpright[ LAYER_CLASS_COPPER ], true ) );
717 
718  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "EdgeCutLineWidth" ),
720  Millimeter2iu( DEFAULT_SILK_LINE_WIDTH ), Millimeter2iu( 0.01 ), Millimeter2iu( 5.0 ),
721  nullptr, MM_PER_IU, wxT( "BoardOutlineThickness" ) ) );
722 
723  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "CourtyardLineWidth" ),
725  Millimeter2iu( DEFAULT_SILK_LINE_WIDTH ), Millimeter2iu( 0.01 ), Millimeter2iu( 5.0 ),
726  nullptr, MM_PER_IU ) );
727 
728  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "OthersLineWidth" ),
730  Millimeter2iu( DEFAULT_SILK_LINE_WIDTH ), Millimeter2iu( 0.01 ), Millimeter2iu( 5.0 ),
731  nullptr, MM_PER_IU, wxT( "ModuleOutlineThickness" ) ) );
732 
733  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "OthersTextSizeV" ),
736  nullptr, MM_PER_IU ) );
737 
738  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "OthersTextSizeH" ),
741  nullptr, MM_PER_IU ) );
742 
743  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "OthersTextSizeThickness" ),
745  Millimeter2iu( DEFAULT_TEXT_WIDTH ), 1, TEXTS_MAX_WIDTH,
746  nullptr, MM_PER_IU ) );
747 
748  aResult->push_back( new PARAM_CFG_BOOL( wxT( "OthersTextItalic" ),
749  &m_TextItalic[ LAYER_CLASS_OTHERS ], false ) );
750 
751  aResult->push_back( new PARAM_CFG_BOOL( wxT( "OthersTextUpright" ),
752  &m_TextUpright[ LAYER_CLASS_OTHERS ], true ) );
753 
754  aResult->push_back( new PARAM_CFG_INT( wxT( "DimensionUnits" ),
755  &m_DimensionUnits, 0, 0, 2 ) );
756  aResult->push_back( new PARAM_CFG_INT( wxT( "DimensionPrecision" ),
757  &m_DimensionPrecision, 1, 0, 2 ) );
758 
759  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "SolderMaskClearance" ),
761  Millimeter2iu( DEFAULT_SOLDERMASK_CLEARANCE ), Millimeter2iu( -1.0 ), Millimeter2iu( 1.0 ),
762  nullptr, MM_PER_IU ) );
763 
764  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "SolderMaskMinWidth" ),
766  Millimeter2iu( DEFAULT_SOLDERMASK_MIN_WIDTH ), 0, Millimeter2iu( 1.0 ),
767  nullptr, MM_PER_IU ) );
768 
769  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "SolderPasteClearance" ),
771  Millimeter2iu( DEFAULT_SOLDERPASTE_CLEARANCE ), Millimeter2iu( -1.0 ), Millimeter2iu( 1.0 ),
772  nullptr, MM_PER_IU ) );
773 
774  aResult->push_back( new PARAM_CFG_DOUBLE( wxT( "SolderPasteRatio" ),
776  DEFAULT_SOLDERPASTE_RATIO, -0.5, 1.0 ) );
777 }
#define DEFAULT_SILK_TEXT_WIDTH
int m_SolderMaskMargin
Solder mask margin.
#define DEFAULT_TRACKMINWIDTH
#define DEFAULT_SOLDERPASTE_RATIO
int m_SolderPasteMargin
Solder paste margin absolute value.
#define DEFAULT_VIASMINSIZE
#define TEXTS_MAX_WIDTH
Maximum text width in internal units (10 inches)
Definition: pcbnew.h:40
std::vector< int > m_TrackWidthList
std::vector< DIFF_PAIR_DIMENSION > m_DiffPairDimensionsList
Configuration parameter - Double Precision Class.
#define LEGACY_COPPEREDGECLEARANCE
#define DEFAULT_HOLETOHOLEMIN
Configuration parameter - Integer Class with unit conversion.
#define DEFAULT_SOLDERPASTE_CLEARANCE
#define DEFAULT_TEXT_WIDTH
wxSize m_TextSize[LAYER_CLASS_COUNT]
#define DEFAULT_SILK_TEXT_SIZE
int m_TextThickness[LAYER_CLASS_COUNT]
#define DEFAULT_SILK_LINE_WIDTH
Configuration parameter - Integer Class.
bool m_TextItalic[LAYER_CLASS_COUNT]
Configuration parameter - Boolean Class.
bool m_BlindBuriedViaAllowed
true to allow blind/buried vias
#define TEXTS_MAX_SIZE
Maximum text size in internal units (10 inches)
Definition: pcbnew.h:39
#define DEFAULT_MICROVIASMINSIZE
#define DEFAULT_MICROVIASMINDRILL
#define DEFAULT_SOLDERMASK_MIN_WIDTH
int m_LineThickness[LAYER_CLASS_COUNT]
#define TEXTS_MIN_SIZE
Minimum text size in internal units (1 mil)
Definition: pcbnew.h:38
#define DEFAULT_COPPER_TEXT_WIDTH
std::vector< VIA_DIMENSION > m_ViasDimensionsList
#define DEFAULT_SOLDERMASK_CLEARANCE
#define DEFAULT_COPPER_TEXT_SIZE
bool m_MicroViasAllowed
true to allow micro vias
double m_SolderPasteMarginRatio
Solder pask margin ratio value of pad size The final margin is the sum of these 2 values.
#define DEFAULT_TEXT_SIZE
#define DEFAULT_VIASMINDRILL
bool m_TextUpright[LAYER_CLASS_COUNT]
int m_SolderMaskMinWidth
Solder mask min width.

References DEFAULT_COPPER_TEXT_SIZE, DEFAULT_COPPER_TEXT_WIDTH, DEFAULT_HOLETOHOLEMIN, DEFAULT_MICROVIASMINDRILL, DEFAULT_MICROVIASMINSIZE, DEFAULT_SILK_LINE_WIDTH, DEFAULT_SILK_TEXT_SIZE, DEFAULT_SILK_TEXT_WIDTH, DEFAULT_SOLDERMASK_CLEARANCE, DEFAULT_SOLDERMASK_MIN_WIDTH, DEFAULT_SOLDERPASTE_CLEARANCE, DEFAULT_SOLDERPASTE_RATIO, DEFAULT_TEXT_SIZE, DEFAULT_TEXT_WIDTH, DEFAULT_TRACKMINWIDTH, DEFAULT_VIASMINDRILL, DEFAULT_VIASMINSIZE, LAYER_CLASS_COPPER, LAYER_CLASS_COURTYARD, LAYER_CLASS_EDGES, LAYER_CLASS_OTHERS, LAYER_CLASS_SILK, LEGACY_COPPEREDGECLEARANCE, m_BlindBuriedViaAllowed, m_CopperEdgeClearance, m_DiffPairDimensionsList, m_DimensionPrecision, m_DimensionUnits, m_HoleToHoleMin, m_LineThickness, m_MicroViasAllowed, m_MicroViasMinDrill, m_MicroViasMinSize, m_NetClasses, m_SolderMaskMargin, m_SolderMaskMinWidth, m_SolderPasteMargin, m_SolderPasteMarginRatio, m_TextItalic, m_TextSize, m_TextThickness, m_TextUpright, m_TrackMinWidth, m_TrackWidthList, m_ViasDimensionsList, m_ViasMinDrill, m_ViasMinSize, TEXTS_MAX_SIZE, TEXTS_MAX_WIDTH, and TEXTS_MIN_SIZE.

Referenced by PCB_EDIT_FRAME::GetProjectFileParameters(), and DIALOG_BOARD_SETUP::OnAuxiliaryAction().

◆ formatNetClass()

void BOARD_DESIGN_SETTINGS::formatNetClass ( NETCLASS aNetClass,
OUTPUTFORMATTER aFormatter,
int  aNestLevel,
int  aControlBits 
) const
private

◆ GetBiggestClearanceValue()

int BOARD_DESIGN_SETTINGS::GetBiggestClearanceValue ( )

Function GetBiggestClearanceValue.

Returns
the biggest clearance value found in NetClasses list

Definition at line 874 of file board_design_settings.cpp.

875 {
876  int clearance = m_NetClasses.GetDefault()->GetClearance();
877 
878  //Read list of Net Classes
879  for( NETCLASSES::const_iterator nc = m_NetClasses.begin(); nc != m_NetClasses.end(); ++nc )
880  {
881  NETCLASSPTR netclass = nc->second;
882  clearance = std::max( clearance, netclass->GetClearance() );
883  }
884 
885  return clearance;
886 }
iterator end()
Definition: netclass.h:249
NETCLASS_MAP::const_iterator const_iterator
Definition: netclass.h:251
iterator begin()
Definition: netclass.h:248
NETCLASSPTR GetDefault() const
Function GetDefault.
Definition: netclass.h:268

References NETCLASSES::begin(), NETCLASSES::end(), NETCLASSES::GetDefault(), and m_NetClasses.

Referenced by ZONE_FILLER::buildCopperItemClearances(), ZONE_FILLER::buildThermalSpokes(), MODULE::GetBoundingPoly(), PNS_KICAD_IFACE_BASE::SyncWorld(), and MODULE::ViewBBox().

◆ GetBoardThickness()

◆ GetCopperLayerCount()

int BOARD_DESIGN_SETTINGS::GetCopperLayerCount ( ) const
inline

Function GetCopperLayerCount.

Returns
int - the number of neabled copper layers

Definition at line 814 of file board_design_settings.h.

815  {
816  return m_copperLayerCount;
817  }
int m_copperLayerCount
Number of copper layers for this design.

References m_copperLayerCount.

Referenced by BOARD_STACKUP::BuildDefaultStackupList(), PANEL_SETUP_BOARD_STACKUP::buildLayerStackPanel(), DRC::doTrackDrc(), BOARD::GetCopperLayerCount(), and ROUTER_TOOL::onViaCommand().

◆ GetCurrentDiffPairGap()

int BOARD_DESIGN_SETTINGS::GetCurrentDiffPairGap ( ) const
inline

Function GetCurrentDiffPairGap.

Returns
the current diff pair gap, according to the selected options ( using the default netclass value or a preset/custom value ) the default netclass is always in m_DiffPairDimensionsList[0]

Definition at line 658 of file board_design_settings.h.

659  {
660  if( m_useCustomDiffPair )
661  return m_customDiffPair.m_Gap;
662  else
664  }
std::vector< DIFF_PAIR_DIMENSION > m_DiffPairDimensionsList
DIFF_PAIR_DIMENSION m_customDiffPair

References m_diffPairIndex, and DIFF_PAIR_DIMENSION::m_Gap.

Referenced by PNS::SIZES_SETTINGS::ImportCurrent().

◆ GetCurrentDiffPairViaGap()

int BOARD_DESIGN_SETTINGS::GetCurrentDiffPairViaGap ( ) const
inline

Function GetCurrentDiffPairViaGap.

Returns
the current diff pair via gap, according to the selected options ( using the default netclass value or a preset/custom value ) the default netclass is always in m_DiffPairDimensionsList[0]

Definition at line 672 of file board_design_settings.h.

673  {
674  if( m_useCustomDiffPair )
675  return m_customDiffPair.m_ViaGap;
676  else
677  return m_DiffPairDimensionsList[m_diffPairIndex].m_ViaGap;
678  }
std::vector< DIFF_PAIR_DIMENSION > m_DiffPairDimensionsList
DIFF_PAIR_DIMENSION m_customDiffPair

References m_diffPairIndex, and DIFF_PAIR_DIMENSION::m_ViaGap.

Referenced by PNS::SIZES_SETTINGS::ImportCurrent().

◆ GetCurrentDiffPairWidth()

int BOARD_DESIGN_SETTINGS::GetCurrentDiffPairWidth ( ) const
inline

Function GetCurrentDiffPairWidth.

Returns
the current diff pair track width, according to the selected options ( using the default netclass value or a preset/custom value ) the default netclass is always in m_DiffPairDimensionsList[0]

Definition at line 644 of file board_design_settings.h.

645  {
646  if( m_useCustomDiffPair )
647  return m_customDiffPair.m_Width;
648  else
650  }
std::vector< DIFF_PAIR_DIMENSION > m_DiffPairDimensionsList
DIFF_PAIR_DIMENSION m_customDiffPair

References m_diffPairIndex, and DIFF_PAIR_DIMENSION::m_Width.

Referenced by PNS::SIZES_SETTINGS::ImportCurrent().

◆ GetCurrentMicroViaDrill()

int BOARD_DESIGN_SETTINGS::GetCurrentMicroViaDrill ( )

Function GetCurrentMicroViaDrill.

Returns
the current micro via drill, that is the current netclass value

Definition at line 912 of file board_design_settings.cpp.

913 {
914  NETCLASSPTR netclass = m_NetClasses.Find( m_currentNetClassName );
915 
916  return netclass->GetuViaDrill();
917 }
wxString m_currentNetClassName
Current net class name used to display netclass info.
NETCLASSPTR Find(const wxString &aName) const
Function Find searches this container for a NETCLASS given by aName.
Definition: netclass.cpp:141

References NETCLASSES::Find(), m_currentNetClassName, and m_NetClasses.

Referenced by ROUTER_TOOL::onViaCommand().

◆ GetCurrentMicroViaSize()

int BOARD_DESIGN_SETTINGS::GetCurrentMicroViaSize ( )

Function GetCurrentMicroViaSize.

Returns
the current micro via size, that is the current netclass value

Definition at line 904 of file board_design_settings.cpp.

905 {
906  NETCLASSPTR netclass = m_NetClasses.Find( m_currentNetClassName );
907 
908  return netclass->GetuViaDiameter();
909 }
wxString m_currentNetClassName
Current net class name used to display netclass info.
NETCLASSPTR Find(const wxString &aName) const
Function Find searches this container for a NETCLASS given by aName.
Definition: netclass.cpp:141

References NETCLASSES::Find(), m_currentNetClassName, and m_NetClasses.

Referenced by ROUTER_TOOL::onViaCommand().

◆ GetCurrentNetClassName()

const wxString& BOARD_DESIGN_SETTINGS::GetCurrentNetClassName ( ) const
inline

Function GetCurrentNetClassName.

Returns
the current net class name.

Definition at line 331 of file board_design_settings.h.

332  {
333  return m_currentNetClassName;
334  }
wxString m_currentNetClassName
Current net class name used to display netclass info.

References m_currentNetClassName.

Referenced by DIALOG_GLOBAL_EDIT_TRACKS_AND_VIAS::buildFilterLists().

◆ GetCurrentTrackWidth()

int BOARD_DESIGN_SETTINGS::GetCurrentTrackWidth ( ) const
inline

Function GetCurrentTrackWidth.

Returns
the current track width, according to the selected options ( using the default netclass value or a preset/custom value ) the default netclass is always in m_TrackWidthList[0]

Definition at line 419 of file board_design_settings.h.

References m_customTrackWidth, and m_trackWidthIndex.

Referenced by BOARD::BOARD(), EDIT_TOOL::ChangeTrackWidth(), PCB_EDIT_FRAME::Create_MuWaveComponent(), MICROWAVE_TOOL::createInductorBetween(), PCB_EDIT_FRAME::CreateMuWaveBaseFootprint(), PCB_IO::formatSetup(), PNS::SIZES_SETTINGS::ImportCurrent(), PNS::SIZES_SETTINGS::Init(), and PCB_EDIT_FRAME::SetTrackSegmentWidth().

◆ GetCurrentViaDrill()

int BOARD_DESIGN_SETTINGS::GetCurrentViaDrill ( ) const

Function GetCurrentViaDrill.

Returns
the current via size, according to the selected options ( using the default netclass value or a preset/custom value ) the default netclass is always in m_TrackWidthList[0]

Definition at line 927 of file board_design_settings.cpp.

928 {
929  int drill;
930 
931  if( m_useCustomTrackVia )
932  drill = m_customViaSize.m_Drill;
933  else
934  drill = m_ViasDimensionsList[m_viaSizeIndex].m_Drill;
935 
936  return drill > 0 ? drill : -1;
937 }
std::vector< VIA_DIMENSION > m_ViasDimensionsList

References m_customViaSize, VIA_DIMENSION::m_Drill, m_useCustomTrackVia, m_ViasDimensionsList, and m_viaSizeIndex.

Referenced by BOARD::BOARD(), EDIT_TOOL::ChangeTrackWidth(), PNS::SIZES_SETTINGS::ImportCurrent(), PNS::SIZES_SETTINGS::Init(), ROUTER_TOOL::onViaCommand(), and PCB_EDIT_FRAME::SetTrackSegmentWidth().

◆ GetCurrentViaSize()

int BOARD_DESIGN_SETTINGS::GetCurrentViaSize ( ) const
inline

Function GetCurrentViaSize.

Returns
the current via size, according to the selected options ( using the default netclass value or a preset/custom value ) the default netclass is always in m_TrackWidthList[0]

Definition at line 468 of file board_design_settings.h.

469  {
470  if( m_useCustomTrackVia )
472  else
473  return m_ViasDimensionsList[m_viaSizeIndex].m_Diameter;
474  }
std::vector< VIA_DIMENSION > m_ViasDimensionsList

References VIA_DIMENSION::m_Diameter, and m_viaSizeIndex.

Referenced by BOARD::BOARD(), EDIT_TOOL::ChangeTrackWidth(), PNS::SIZES_SETTINGS::ImportCurrent(), PNS::SIZES_SETTINGS::Init(), ROUTER_TOOL::onViaCommand(), and PCB_EDIT_FRAME::SetTrackSegmentWidth().

◆ GetCustomDiffPairGap()

int BOARD_DESIGN_SETTINGS::GetCustomDiffPairGap ( )
inline

Function GetCustomDiffPairGap.

Returns
Current custom gap width for differential pairs.

Definition at line 594 of file board_design_settings.h.

595  {
596  return m_customDiffPair.m_Gap;
597  }
DIFF_PAIR_DIMENSION m_customDiffPair

References DIFF_PAIR_DIMENSION::m_Gap.

Referenced by PNS::SIZES_SETTINGS::Init().

◆ GetCustomDiffPairViaGap()

int BOARD_DESIGN_SETTINGS::GetCustomDiffPairViaGap ( )
inline

Function GetCustomDiffPairViaGap.

Returns
Current custom via gap width for differential pairs.

Definition at line 614 of file board_design_settings.h.

References DIFF_PAIR_DIMENSION::m_Gap, and DIFF_PAIR_DIMENSION::m_ViaGap.

Referenced by PNS::SIZES_SETTINGS::Init().

◆ GetCustomDiffPairWidth()

int BOARD_DESIGN_SETTINGS::GetCustomDiffPairWidth ( )
inline

Function GetCustomDiffPairWidth.

Returns
Current custom track width for differential pairs.

Definition at line 574 of file board_design_settings.h.

575  {
576  return m_customDiffPair.m_Width;
577  }
DIFF_PAIR_DIMENSION m_customDiffPair

References DIFF_PAIR_DIMENSION::m_Width.

Referenced by PNS::SIZES_SETTINGS::Init().

◆ GetCustomTrackWidth()

int BOARD_DESIGN_SETTINGS::GetCustomTrackWidth ( ) const
inline

Function GetCustomTrackWidth.

Returns
Current custom width for a track.

Definition at line 440 of file board_design_settings.h.

441  {
442  return m_customTrackWidth;
443  }

References m_customTrackWidth.

Referenced by DIALOG_TRACK_VIA_SIZE::TransferDataToWindow().

◆ GetCustomViaDrill()

int BOARD_DESIGN_SETTINGS::GetCustomViaDrill ( ) const
inline

Function GetCustomViaDrill.

Returns
Current custom size for the via drill.

Definition at line 521 of file board_design_settings.h.

522  {
523  return m_customViaSize.m_Drill;
524  }

References VIA_DIMENSION::m_Drill.

Referenced by DIALOG_TRACK_VIA_SIZE::TransferDataToWindow().

◆ GetCustomViaSize()

int BOARD_DESIGN_SETTINGS::GetCustomViaSize ( ) const
inline

Function GetCustomViaSize.

Returns
Current custom size for the via diameter.

Definition at line 492 of file board_design_settings.h.

493  {
495  }

References VIA_DIMENSION::m_Diameter.

Referenced by DIALOG_TRACK_VIA_SIZE::TransferDataToWindow().

◆ GetDefault()

◆ GetDiffPairIndex()

unsigned BOARD_DESIGN_SETTINGS::GetDiffPairIndex ( ) const
inline

Function GetDiffPairIndex.

Returns
the current diff pair dimension list index.

Definition at line 551 of file board_design_settings.h.

551 { return m_diffPairIndex; }

References m_diffPairIndex.

Referenced by PNS::SIZES_SETTINGS::Init(), SetCurrentNetClass(), and DIFF_PAIR_MENU::update().

◆ GetEnabledLayers()

LSET BOARD_DESIGN_SETTINGS::GetEnabledLayers ( ) const
inline

Function GetEnabledLayers returns a bit-mask of all the layers that are enabled.

Returns
int - the enabled layers in bit-mapped form.

Definition at line 787 of file board_design_settings.h.

788  {
789  return m_enabledLayers;
790  }
LSET m_enabledLayers
Bit-mask for layer enabling.

References m_enabledLayers.

Referenced by BOARD_STACKUP::BuildDefaultStackupList(), CreatePadsShapesSection(), CreateRoutesSection(), BOARD::GetEnabledLayers(), PARAM_CFG_LAYERS::ReadParam(), and HYPERLYNX_EXPORTER::writeStackupInfo().

◆ GetLayerClass()

int BOARD_DESIGN_SETTINGS::GetLayerClass ( PCB_LAYER_ID  aLayer) const

◆ GetLineThickness()

int BOARD_DESIGN_SETTINGS::GetLineThickness ( PCB_LAYER_ID  aLayer) const

Function GetLineThickness Returns the default graphic segment thickness from the layer class for the given layer.

Definition at line 1045 of file board_design_settings.cpp.

1046 {
1047  return m_LineThickness[ GetLayerClass( aLayer ) ];
1048 }
int GetLayerClass(PCB_LAYER_ID aLayer) const
int m_LineThickness[LAYER_CLASS_COUNT]

References GetLayerClass(), and m_LineThickness.

Referenced by DRAWING_TOOL::DrawDimension(), DRAWING_TOOL::getSegmentWidth(), EAGLE_PLUGIN::loadPlain(), DIALOG_PAD_PROPERTIES::onAddPrimitive(), EAGLE_PLUGIN::packageWire(), PCB_EDITOR_CONTROL::PlaceTarget(), and DIALOG_GLOBAL_EDIT_TEXT_AND_GRAPHICS::processItem().

◆ GetSeverity()

int BOARD_DESIGN_SETTINGS::GetSeverity ( int  aDRCErrorCode)

◆ GetSmallestClearanceValue()

int BOARD_DESIGN_SETTINGS::GetSmallestClearanceValue ( )

Function GetSmallestClearanceValue.

Returns
the smallest clearance value found in NetClasses list

Definition at line 889 of file board_design_settings.cpp.

890 {
891  int clearance = m_NetClasses.GetDefault()->GetClearance();
892 
893  //Read list of Net Classes
894  for( NETCLASSES::const_iterator nc = m_NetClasses.begin(); nc != m_NetClasses.end(); ++nc )
895  {
896  NETCLASSPTR netclass = nc->second;
897  clearance = std::min( clearance, netclass->GetClearance() );
898  }
899 
900  return clearance;
901 }
iterator end()
Definition: netclass.h:249
NETCLASS_MAP::const_iterator const_iterator
Definition: netclass.h:251
iterator begin()
Definition: netclass.h:248
NETCLASSPTR GetDefault() const
Function GetDefault.
Definition: netclass.h:268

References NETCLASSES::begin(), NETCLASSES::end(), NETCLASSES::GetDefault(), and m_NetClasses.

Referenced by DIALOG_PLOT::init_Dialog().

◆ GetStackupDescriptor()

◆ GetTextItalic()

◆ GetTextSize()

wxSize BOARD_DESIGN_SETTINGS::GetTextSize ( PCB_LAYER_ID  aLayer) const

Function GetTextSize Returns the default text size from the layer class for the given layer.

Definition at line 1051 of file board_design_settings.cpp.

1052 {
1053  return m_TextSize[ GetLayerClass( aLayer ) ];
1054 }
int GetLayerClass(PCB_LAYER_ID aLayer) const
wxSize m_TextSize[LAYER_CLASS_COUNT]

References GetLayerClass(), and m_TextSize.

Referenced by PCB_BASE_FRAME::CreateNewModule(), DRAWING_TOOL::DrawDimension(), EAGLE_PLUGIN::loadPlain(), DIALOG_FOOTPRINT_FP_EDITOR::OnAddField(), DIALOG_FOOTPRINT_BOARD_EDITOR::OnAddField(), DRAWING_TOOL::PlaceText(), and DIALOG_GLOBAL_EDIT_TEXT_AND_GRAPHICS::processItem().

◆ GetTextThickness()

int BOARD_DESIGN_SETTINGS::GetTextThickness ( PCB_LAYER_ID  aLayer) const

Function GetTextThickness Returns the default text thickness from the layer class for the given layer.

Definition at line 1057 of file board_design_settings.cpp.

1058 {
1059  return m_TextThickness[ GetLayerClass( aLayer ) ];
1060 }
int GetLayerClass(PCB_LAYER_ID aLayer) const
int m_TextThickness[LAYER_CLASS_COUNT]

References GetLayerClass(), and m_TextThickness.

Referenced by PCB_BASE_FRAME::CreateNewModule(), DRAWING_TOOL::DrawDimension(), EAGLE_PLUGIN::loadPlain(), DIALOG_FOOTPRINT_FP_EDITOR::OnAddField(), DIALOG_FOOTPRINT_BOARD_EDITOR::OnAddField(), DRAWING_TOOL::PlaceText(), and DIALOG_GLOBAL_EDIT_TEXT_AND_GRAPHICS::processItem().

◆ GetTextUpright()

bool BOARD_DESIGN_SETTINGS::GetTextUpright ( PCB_LAYER_ID  aLayer) const

◆ GetTrackWidthIndex()

unsigned BOARD_DESIGN_SETTINGS::GetTrackWidthIndex ( ) const
inline

◆ GetViaSizeIndex()

unsigned BOARD_DESIGN_SETTINGS::GetViaSizeIndex ( ) const
inline

◆ GetVisibleElements()

int BOARD_DESIGN_SETTINGS::GetVisibleElements ( ) const
inline

Function GetVisibleElements returns a bit-mask of all the element categories that are visible.

Returns
int - the visible element categories in bit-mapped form.

Definition at line 745 of file board_design_settings.h.

746  {
747  return m_visibleElements;
748  }
int m_visibleElements
Bit-mask for element category visibility.

References m_visibleElements.

Referenced by PCB_IO::formatSetup(), and BOARD::GetVisibleElements().

◆ GetVisibleLayers()

LSET BOARD_DESIGN_SETTINGS::GetVisibleLayers ( ) const
inline

Function GetVisibleLayers returns a bit-mask of all the layers that are visible.

Returns
int - the visible layers in bit-mapped form.

Definition at line 698 of file board_design_settings.h.

699  {
700  return m_visibleLayers;
701  }
LSET m_visibleLayers
Bit-mask for layer visibility.

References m_visibleLayers.

Referenced by BOARD::GetVisibleLayers().

◆ Ignore()

bool BOARD_DESIGN_SETTINGS::Ignore ( int  aDRCErrorCode)

returns true if the DRC error code's severity is SEVERITY_IGNORE

Definition at line 786 of file board_design_settings.cpp.

787 {
788  return m_DRCSeverities[ aDRCErrorCode ] == RPT_SEVERITY_IGNORE;
789 }
std::map< int, int > m_DRCSeverities

References m_DRCSeverities, and RPT_SEVERITY_IGNORE.

Referenced by DRC_COURTYARD_OVERLAP::RunDRC(), and DRC::RunTests().

◆ IsElementVisible()

bool BOARD_DESIGN_SETTINGS::IsElementVisible ( GAL_LAYER_ID  aElementCategory) const
inline

Function IsElementVisible tests whether a given element category is visible.

Keep this as an inline function.

Parameters
aElementCategoryis from the enum by the same name
Returns
bool - true if the element is visible.
See also
enum GAL_LAYER_ID

Definition at line 768 of file board_design_settings.h.

769  {
770  return ( m_visibleElements & ( 1 << GAL_LAYER_INDEX( aElementCategory ) ) );
771  }
#define GAL_LAYER_INDEX(x)
Use this macro to convert a GAL layer to a 0-indexed offset from LAYER_VIAS.
int m_visibleElements
Bit-mask for element category visibility.

References GAL_LAYER_INDEX.

Referenced by BOARD::IsElementVisible().

◆ IsLayerEnabled()

bool BOARD_DESIGN_SETTINGS::IsLayerEnabled ( PCB_LAYER_ID  aLayerId) const
inline

Function IsLayerEnabled tests whether a given layer is enabled.

Parameters
aLayerId= The layer to be tested
Returns
bool - true if the layer is enabled

Definition at line 805 of file board_design_settings.h.

806  {
807  return m_enabledLayers[aLayerId];
808  }
LSET m_enabledLayers
Bit-mask for layer enabling.

Referenced by BOARD::IsLayerEnabled(), and SetLayerVisibility().

◆ IsLayerVisible()

bool BOARD_DESIGN_SETTINGS::IsLayerVisible ( PCB_LAYER_ID  aLayerId) const
inline

Function IsLayerVisible tests whether a given layer is visible.

Parameters
aLayerId= The layer to be tested
Returns
bool - true if the layer is visible.

Definition at line 726 of file board_design_settings.h.

727  {
728  // If a layer is disabled, it is automatically invisible
729  return (m_visibleLayers & m_enabledLayers)[aLayerId];
730  }
LSET m_visibleLayers
Bit-mask for layer visibility.
LSET m_enabledLayers
Bit-mask for layer enabling.

Referenced by CINFO3D_VISU::Is3DLayerEnabled(), and BOARD::IsLayerVisible().

◆ SetBoardThickness()

void BOARD_DESIGN_SETTINGS::SetBoardThickness ( int  aThickness)
inline

◆ SetCopperEdgeClearance()

void BOARD_DESIGN_SETTINGS::SetCopperEdgeClearance ( int  aDistance)

Function SetCopperEdgeClearance.

Parameters
aValueThe minimum distance between copper items and board edges.

Definition at line 960 of file board_design_settings.cpp.

961 {
962  m_CopperEdgeClearance = aDistance;
963 }

References m_CopperEdgeClearance.

Referenced by PCB_EDIT_FRAME::OpenProjectFiles(), and PANEL_SETUP_FEATURE_CONSTRAINTS::TransferDataFromWindow().

◆ SetCopperLayerCount()

void BOARD_DESIGN_SETTINGS::SetCopperLayerCount ( int  aNewLayerCount)

Function SetCopperLayerCount do what its name says...

Parameters
aNewLayerCount= The new number of enabled copper layers

Definition at line 988 of file board_design_settings.cpp.

989 {
990  // if( aNewLayerCount < 2 ) aNewLayerCount = 2;
991 
992  m_copperLayerCount = aNewLayerCount;
993 
994  // ensure consistency with the m_EnabledLayers member
995 #if 0
996  // was:
999 
1000  if( m_copperLayerCount > 1 )
1002 
1003  for( LAYER_NUM ii = LAYER_N_2; ii < aNewLayerCount - 1; ++ii )
1004  m_enabledLayers |= GetLayerSet( ii );
1005 #else
1006  // Update only enabled copper layers mask
1007  m_enabledLayers &= ~LSET::AllCuMask();
1008  m_enabledLayers |= LSET::AllCuMask( aNewLayerCount );
1009 #endif
1010 }
static LSET AllCuMask(int aCuLayerCount=MAX_CU_LAYERS)
Function AllCuMask returns a mask holding the requested number of Cu PCB_LAYER_IDs.
Definition: lset.cpp:686
#define LAYER_FRONT
bit mask for component layer
LSET is a set of PCB_LAYER_IDs.
#define ALL_CU_LAYERS
int LAYER_NUM
Type LAYER_NUM can be replaced with int and removed.
#define LAYER_BACK
bit mask for copper layer
#define LAYER_N_2
int m_copperLayerCount
Number of copper layers for this design.
LSET m_enabledLayers
Bit-mask for layer enabling.

References ALL_CU_LAYERS, LSET::AllCuMask(), LAYER_BACK, LAYER_FRONT, LAYER_N_2, m_copperLayerCount, and m_enabledLayers.

Referenced by BOARD_DESIGN_SETTINGS(), PARAM_CFG_LAYERS::ReadParam(), and BOARD::SetCopperLayerCount().

◆ SetCurrentNetClass()

bool BOARD_DESIGN_SETTINGS::SetCurrentNetClass ( const wxString &  aNetClassName)

Function SetCurrentNetClass Must be called after a netclass selection (or after a netclass parameter change Initialize vias and tracks values displayed in comb boxes of the auxiliary toolbar and some others parameters (netclass name ....)

Parameters
aNetClassName= the new netclass name
Returns
true if lists of tracks and vias sizes are modified

Definition at line 792 of file board_design_settings.cpp.

793 {
794  NETCLASSPTR netClass = m_NetClasses.Find( aNetClassName );
795  bool lists_sizes_modified = false;
796 
797  // if not found (should not happen) use the default
798  if( !netClass )
799  netClass = m_NetClasses.GetDefault();
800 
801  m_currentNetClassName = netClass->GetName();
802 
803  // Initialize others values:
804  if( m_TrackWidthList.size() == 0 )
805  {
806  lists_sizes_modified = true;
807  m_TrackWidthList.push_back( 0 );
808  }
809 
810  if( m_ViasDimensionsList.size() == 0 )
811  {
812  lists_sizes_modified = true;
813  m_ViasDimensionsList.emplace_back( VIA_DIMENSION() );
814  }
815 
816  if( m_DiffPairDimensionsList.size() == 0 )
817  {
818  lists_sizes_modified = true;
820  }
821 
822  /* note the m_ViasDimensionsList[0] and m_TrackWidthList[0] values
823  * are always the Netclass values
824  */
825  if( m_TrackWidthList[0] != netClass->GetTrackWidth() )
826  {
827  lists_sizes_modified = true;
828  m_TrackWidthList[0] = netClass->GetTrackWidth();
829  }
830 
831  if( m_ViasDimensionsList[0].m_Diameter != netClass->GetViaDiameter() )
832  {
833  lists_sizes_modified = true;
834  m_ViasDimensionsList[0].m_Diameter = netClass->GetViaDiameter();
835  }
836 
837  if( m_ViasDimensionsList[0].m_Drill != netClass->GetViaDrill() )
838  {
839  lists_sizes_modified = true;
840  m_ViasDimensionsList[0].m_Drill = netClass->GetViaDrill();
841  }
842 
843  if( m_DiffPairDimensionsList[0].m_Width != netClass->GetDiffPairWidth() )
844  {
845  lists_sizes_modified = true;
846  m_DiffPairDimensionsList[0].m_Width = netClass->GetDiffPairWidth();
847  }
848 
849  if( m_DiffPairDimensionsList[0].m_Gap != netClass->GetDiffPairGap() )
850  {
851  lists_sizes_modified = true;
852  m_DiffPairDimensionsList[0].m_Gap = netClass->GetDiffPairGap();
853  }
854 
855  if( m_DiffPairDimensionsList[0].m_ViaGap != netClass->GetDiffPairViaGap() )
856  {
857  lists_sizes_modified = true;
858  m_DiffPairDimensionsList[0].m_ViaGap = netClass->GetDiffPairViaGap();
859  }
860 
861  if( GetViaSizeIndex() >= m_ViasDimensionsList.size() )
863 
864  if( GetTrackWidthIndex() >= m_TrackWidthList.size() )
866 
869 
870  return lists_sizes_modified;
871 }
Struct VIA_DIMENSION is a small helper container to handle a stock of specific vias each with unique ...
void SetTrackWidthIndex(unsigned aIndex)
Function SetTrackWidthIndex sets the current track width list index to aIndex.
wxString m_currentNetClassName
Current net class name used to display netclass info.
NETCLASSPTR Find(const wxString &aName) const
Function Find searches this container for a NETCLASS given by aName.
Definition: netclass.cpp:141
std::vector< int > m_TrackWidthList
std::vector< DIFF_PAIR_DIMENSION > m_DiffPairDimensionsList
Struct DIFF_PAIR_DIMENSION is a small helper container to handle a stock of specific differential pai...
void SetViaSizeIndex(unsigned aIndex)
Function SetViaSizeIndex sets the current via size list index to aIndex.
unsigned GetViaSizeIndex() const
Function GetViaSizeIndex.
unsigned GetTrackWidthIndex() const
Function GetTrackWidthIndex.
void SetDiffPairIndex(unsigned aIndex)
Function SetDiffPairIndex.
std::vector< VIA_DIMENSION > m_ViasDimensionsList
NETCLASSPTR GetDefault() const
Function GetDefault.
Definition: netclass.h:268
unsigned GetDiffPairIndex() const
Function GetDiffPairIndex.

References NETCLASSES::Find(), NETCLASSES::GetDefault(), GetDiffPairIndex(), GetTrackWidthIndex(), GetViaSizeIndex(), m_currentNetClassName, m_DiffPairDimensionsList, m_NetClasses, m_TrackWidthList, m_ViasDimensionsList, SetDiffPairIndex(), SetTrackWidthIndex(), and SetViaSizeIndex().

Referenced by BOARD::BOARD(), SaveBoard(), and PANEL_SETUP_NETCLASSES::TransferDataFromWindow().

◆ SetCustomDiffPairGap()

void BOARD_DESIGN_SETTINGS::SetCustomDiffPairGap ( int  aGap)
inline

Function SetCustomDiffPairGap Sets custom gap for differential pairs (i.e.

not available in netclasses or preset list).

Parameters
aGapis the new gap.

Definition at line 585 of file board_design_settings.h.

586  {
587  m_customDiffPair.m_Gap = aGap;
588  }
DIFF_PAIR_DIMENSION m_customDiffPair

References DIFF_PAIR_DIMENSION::m_Gap.

Referenced by ROUTER_TOOL::DpDimensionsDialog(), and BOARD::SynchronizeNetsAndNetClasses().

◆ SetCustomDiffPairViaGap()

void BOARD_DESIGN_SETTINGS::SetCustomDiffPairViaGap ( int  aGap)
inline

Function SetCustomDiffPairViaGap Sets custom via gap for differential pairs (i.e.

not available in netclasses or preset list).

Parameters
aGapis the new gap. Specify 0 to use the DiffPairGap for vias as well.

Definition at line 605 of file board_design_settings.h.

606  {
607  m_customDiffPair.m_ViaGap = aGap;
608  }
DIFF_PAIR_DIMENSION m_customDiffPair

References DIFF_PAIR_DIMENSION::m_ViaGap.

Referenced by ROUTER_TOOL::DpDimensionsDialog(), and BOARD::SynchronizeNetsAndNetClasses().

◆ SetCustomDiffPairWidth()

void BOARD_DESIGN_SETTINGS::SetCustomDiffPairWidth ( int  aWidth)
inline

Function SetCustomDiffPairWidth Sets custom track width for differential pairs (i.e.

not available in netclasses or preset list).

Parameters
aDrillis the new track wdith.

Definition at line 565 of file board_design_settings.h.

566  {
567  m_customDiffPair.m_Width = aWidth;
568  }
DIFF_PAIR_DIMENSION m_customDiffPair

References DIFF_PAIR_DIMENSION::m_Width.

Referenced by ROUTER_TOOL::DpDimensionsDialog(), and BOARD::SynchronizeNetsAndNetClasses().

◆ SetCustomTrackWidth()

void BOARD_DESIGN_SETTINGS::SetCustomTrackWidth ( int  aWidth)
inline

Function SetCustomTrackWidth Sets custom width for track (i.e.

not available in netclasses or preset list). To have it returned with GetCurrentTrackWidth() you need to enable custom track & via sizes (UseCustomTrackViaSize()).

Parameters
aWidthis the new track width.

Definition at line 431 of file board_design_settings.h.

432  {
433  m_customTrackWidth = aWidth;
434  }

Referenced by BOARD::BOARD(), BOARD::SynchronizeNetsAndNetClasses(), and DIALOG_TRACK_VIA_SIZE::TransferDataFromWindow().

◆ SetCustomViaDrill()

void BOARD_DESIGN_SETTINGS::SetCustomViaDrill ( int  aDrill)
inline

Function SetCustomViaDrill Sets custom size for via drill (i.e.

not available in netclasses or preset list). To have it returned with GetCurrentViaDrill() you need to enable custom track & via sizes (UseCustomTrackViaSize()).

Parameters
aDrillis the new drill size.

Definition at line 512 of file board_design_settings.h.

513  {
514  m_customViaSize.m_Drill = aDrill;
515  }

References VIA_DIMENSION::m_Drill.

Referenced by BOARD::BOARD(), BOARD::SynchronizeNetsAndNetClasses(), and DIALOG_TRACK_VIA_SIZE::TransferDataFromWindow().

◆ SetCustomViaSize()

void BOARD_DESIGN_SETTINGS::SetCustomViaSize ( int  aSize)
inline

Function SetCustomViaSize Sets custom size for via diameter (i.e.

not available in netclasses or preset list). To have it returned with GetCurrentViaSize() you need to enable custom track & via sizes (UseCustomTrackViaSize()).

Parameters
aSizeis the new drill diameter.

Definition at line 483 of file board_design_settings.h.

484  {
485  m_customViaSize.m_Diameter = aSize;
486  }

References VIA_DIMENSION::m_Diameter.

Referenced by BOARD::BOARD(), BOARD::SynchronizeNetsAndNetClasses(), and DIALOG_TRACK_VIA_SIZE::TransferDataFromWindow().

◆ SetDiffPairIndex()

void BOARD_DESIGN_SETTINGS::SetDiffPairIndex ( unsigned  aIndex)

Function SetDiffPairIndex.

Parameters
aIndexis the diff pair dimensions list index to set.

Definition at line 947 of file board_design_settings.cpp.

948 {
949  m_diffPairIndex = std::min( aIndex, (unsigned) 8 );
950  m_useCustomDiffPair = false;
951 }

References m_diffPairIndex, and m_useCustomDiffPair.

Referenced by DIFF_PAIR_MENU::eventHandler(), and SetCurrentNetClass().

◆ SetElementVisibility()

void BOARD_DESIGN_SETTINGS::SetElementVisibility ( GAL_LAYER_ID  aElementCategory,
bool  aNewState 
)

Function SetElementVisibility changes the visibility of an element category.

Parameters
aElementCategoryis from the enum by the same name
aNewState= The new visibility state of the element category
See also
enum GAL_LAYER_ID

Definition at line 979 of file board_design_settings.cpp.

980 {
981  if( aNewState )
982  m_visibleElements |= 1 << GAL_LAYER_INDEX( aElementCategory );
983  else
984  m_visibleElements &= ~( 1 << GAL_LAYER_INDEX( aElementCategory ) );
985 }
#define GAL_LAYER_INDEX(x)
Use this macro to convert a GAL layer to a 0-indexed offset from LAYER_VIAS.
int m_visibleElements
Bit-mask for element category visibility.

References GAL_LAYER_INDEX, and m_visibleElements.

Referenced by BOARD::SetElementVisibility().

◆ SetEnabledLayers()

void BOARD_DESIGN_SETTINGS::SetEnabledLayers ( LSET  aMask)

Function SetEnabledLayers changes the bit-mask of enabled layers.

Parameters
aMask= The new bit-mask of enabled layers

Definition at line 1013 of file board_design_settings.cpp.

1014 {
1015  // Back and front layers are always enabled.
1016  aMask.set( B_Cu ).set( F_Cu );
1017 
1018  m_enabledLayers = aMask;
1019 
1020  // A disabled layer cannot be visible
1021  m_visibleLayers &= aMask;
1022 
1023  // update m_CopperLayerCount to ensure its consistency with m_EnabledLayers
1024  m_copperLayerCount = ( aMask & LSET::AllCuMask() ).count();
1025 }
static LSET AllCuMask(int aCuLayerCount=MAX_CU_LAYERS)
Function AllCuMask returns a mask holding the requested number of Cu PCB_LAYER_IDs.
Definition: lset.cpp:686
LSET m_visibleLayers
Bit-mask for layer visibility.
int m_copperLayerCount
Number of copper layers for this design.
LSET m_enabledLayers
Bit-mask for layer enabling.

References LSET::AllCuMask(), B_Cu, F_Cu, m_copperLayerCount, m_enabledLayers, and m_visibleLayers.

Referenced by BOARD::SetEnabledLayers().

◆ SetLayerVisibility()

void BOARD_DESIGN_SETTINGS::SetLayerVisibility ( PCB_LAYER_ID  aLayerId,
bool  aNewState 
)

Function SetLayerVisibility changes the visibility of a given layer.

Parameters
aLayerId= The layer to be changed
aNewState= The new visibility state of the layer

Definition at line 973 of file board_design_settings.cpp.

974 {
975  m_visibleLayers.set( aLayer, aNewState && IsLayerEnabled( aLayer ));
976 }
bool IsLayerEnabled(PCB_LAYER_ID aLayerId) const
Function IsLayerEnabled tests whether a given layer is enabled.
LSET m_visibleLayers
Bit-mask for layer visibility.

References IsLayerEnabled(), and m_visibleLayers.

◆ SetMinHoleSeparation()

void BOARD_DESIGN_SETTINGS::SetMinHoleSeparation ( int  aDistance)

Function SetMinHoleSeparation.

Parameters
aValueThe minimum distance between the edges of two holes or 0 to disable hole-to-hole separation checking.

Definition at line 954 of file board_design_settings.cpp.

955 {
956  m_HoleToHoleMin = aDistance;
957 }

References m_HoleToHoleMin.

Referenced by PANEL_SETUP_FEATURE_CONSTRAINTS::TransferDataFromWindow().

◆ SetTrackWidthIndex()

void BOARD_DESIGN_SETTINGS::SetTrackWidthIndex ( unsigned  aIndex)

Function SetTrackWidthIndex sets the current track width list index to aIndex.

Parameters
aIndexis the track width list index.

Definition at line 940 of file board_design_settings.cpp.

941 {
942  m_trackWidthIndex = std::min( aIndex, (unsigned) m_TrackWidthList.size() );
943  m_useCustomTrackVia = false;
944 }
std::vector< int > m_TrackWidthList

References m_trackWidthIndex, m_TrackWidthList, and m_useCustomTrackVia.

Referenced by TRACK_WIDTH_MENU::eventHandler(), DIALOG_GLOBAL_EDIT_TRACKS_AND_VIAS::processItem(), SetCurrentNetClass(), PCB_EDIT_FRAME::Tracks_and_Vias_Size_Event(), PCB_EDITOR_CONTROL::TrackWidthDec(), PCB_EDITOR_CONTROL::TrackWidthInc(), and PCB_EDIT_FRAME::UpdateTrackWidthSelectBox().

◆ SetViaSizeIndex()

void BOARD_DESIGN_SETTINGS::SetViaSizeIndex ( unsigned  aIndex)

Function SetViaSizeIndex sets the current via size list index to aIndex.

Parameters
aIndexis the via size list index.

Definition at line 920 of file board_design_settings.cpp.

921 {
922  m_viaSizeIndex = std::min( aIndex, (unsigned) m_ViasDimensionsList.size() );
923  m_useCustomTrackVia = false;
924 }
std::vector< VIA_DIMENSION > m_ViasDimensionsList

References m_useCustomTrackVia, m_ViasDimensionsList, and m_viaSizeIndex.

Referenced by TRACK_WIDTH_MENU::eventHandler(), DIALOG_GLOBAL_EDIT_TRACKS_AND_VIAS::processItem(), SetCurrentNetClass(), PCB_EDIT_FRAME::Tracks_and_Vias_Size_Event(), PCB_EDIT_FRAME::UpdateViaSizeSelectBox(), PCB_EDITOR_CONTROL::ViaSizeDec(), and PCB_EDITOR_CONTROL::ViaSizeInc().

◆ SetVisibleAlls()

void BOARD_DESIGN_SETTINGS::SetVisibleAlls ( )

Function SetVisibleAlls Set the bit-mask of all visible elements categories, including enabled layers.

Definition at line 966 of file board_design_settings.cpp.

967 {
968  SetVisibleLayers( LSET().set() );
969  m_visibleElements = -1;
970 }
void SetVisibleLayers(LSET aMask)
Function SetVisibleLayers changes the bit-mask of visible layers.
LSET is a set of PCB_LAYER_IDs.
int m_visibleElements
Bit-mask for element category visibility.

References m_visibleElements, and SetVisibleLayers().

◆ SetVisibleElements()

void BOARD_DESIGN_SETTINGS::SetVisibleElements ( int  aMask)
inline

Function SetVisibleElements changes the bit-mask of visible element categories.

Parameters
aMask= The new bit-mask of visible element categories

Definition at line 755 of file board_design_settings.h.

756  {
757  m_visibleElements = aMask;
758  }
int m_visibleElements
Bit-mask for element category visibility.

Referenced by LEGACY_PLUGIN::loadSETUP(), and PCB_PARSER::parseSetup().

◆ SetVisibleLayers()

void BOARD_DESIGN_SETTINGS::SetVisibleLayers ( LSET  aMask)
inline

Function SetVisibleLayers changes the bit-mask of visible layers.

Parameters
aMask= The new bit-mask of visible layers

Definition at line 715 of file board_design_settings.h.

716  {
718  }
LSET m_visibleLayers
Bit-mask for layer visibility.
LSET m_enabledLayers
Bit-mask for layer enabling.

References m_enabledLayers.

Referenced by BOARD_DESIGN_SETTINGS(), SetVisibleAlls(), and BOARD::SetVisibleLayers().

◆ UseCustomDiffPairDimensions() [1/2]

void BOARD_DESIGN_SETTINGS::UseCustomDiffPairDimensions ( bool  aEnabled)
inline

Function UseCustomDiffPairDimensions Enables/disables custom differential pair dimensions.

Parameters
aEnableddecides if custom settings should be used for new differential pairs.

Definition at line 624 of file board_design_settings.h.

625  {
626  m_useCustomDiffPair = aEnabled;
627  }

Referenced by DIFF_PAIR_MENU::eventHandler(), PNS::SIZES_SETTINGS::Init(), and DIFF_PAIR_MENU::update().

◆ UseCustomDiffPairDimensions() [2/2]

bool BOARD_DESIGN_SETTINGS::UseCustomDiffPairDimensions ( ) const
inline

Function UseCustomDiffPairDimensions.

Returns
True if custom sizes of diff pairs are enabled, false otherwise.

Definition at line 633 of file board_design_settings.h.

634  {
635  return m_useCustomDiffPair;
636  }

References m_useCustomDiffPair.

◆ UseCustomTrackViaSize() [1/2]

void BOARD_DESIGN_SETTINGS::UseCustomTrackViaSize ( bool  aEnabled)
inline

Function UseCustomTrackViaSize Enables/disables custom track/via size settings.

If enabled, values set with SetCustomTrackWidth()/SetCustomViaSize()/SetCustomViaDrill() are used for newly created tracks and vias.

Parameters
aEnableddecides if custom settings should be used for new tracks/vias.

Definition at line 533 of file board_design_settings.h.

534  {
535  m_useCustomTrackVia = aEnabled;
536  }

Referenced by BOARD::BOARD(), ROUTER_TOOL::CustomTrackWidthDialog(), TRACK_WIDTH_MENU::eventHandler(), BOARD::SynchronizeNetsAndNetClasses(), PCB_EDITOR_CONTROL::TrackWidthDec(), PCB_EDITOR_CONTROL::TrackWidthInc(), TRACK_WIDTH_MENU::update(), PCB_EDITOR_CONTROL::ViaSizeDec(), and PCB_EDITOR_CONTROL::ViaSizeInc().

◆ UseCustomTrackViaSize() [2/2]

bool BOARD_DESIGN_SETTINGS::UseCustomTrackViaSize ( ) const
inline

Function UseCustomTrackViaSize.

Returns
True if custom sizes of tracks & vias are enabled, false otherwise.

Definition at line 542 of file board_design_settings.h.

543  {
544  return m_useCustomTrackVia;
545  }

References m_useCustomTrackVia.

◆ UseNetClassDiffPair()

bool BOARD_DESIGN_SETTINGS::UseNetClassDiffPair ( ) const
inline

Function UseNetClassDiffPair returns true if netclass values should be used to obtain appropriate diff pair dimensions.

Definition at line 358 of file board_design_settings.h.

359  {
360  return ( m_diffPairIndex == 0 && !m_useCustomDiffPair );
361  }

Referenced by PNS::SIZES_SETTINGS::Init().

◆ UseNetClassTrack()

bool BOARD_DESIGN_SETTINGS::UseNetClassTrack ( ) const
inline

Function UseNetClassTrack returns true if netclass values should be used to obtain appropriate track width.

Definition at line 340 of file board_design_settings.h.

341  {
342  return ( m_trackWidthIndex == 0 && !m_useCustomTrackVia );
343  }

Referenced by PNS::SIZES_SETTINGS::Init().

◆ UseNetClassVia()

bool BOARD_DESIGN_SETTINGS::UseNetClassVia ( ) const
inline

Function UseNetClassVia returns true if netclass values should be used to obtain appropriate via size.

Definition at line 349 of file board_design_settings.h.

350  {
351  return ( m_viaSizeIndex == 0 && !m_useCustomTrackVia );
352  }

Referenced by PNS::SIZES_SETTINGS::Init().

Member Data Documentation

◆ m_AuxOrigin

wxPoint BOARD_DESIGN_SETTINGS::m_AuxOrigin

origin for plot exports

Definition at line 257 of file board_design_settings.h.

Referenced by BOARD::GetAuxOrigin(), LEGACY_PLUGIN::loadSETUP(), PCB_PARSER::parseSetup(), and BOARD::SetAuxOrigin().

◆ m_BlindBuriedViaAllowed

◆ m_boardThickness

int BOARD_DESIGN_SETTINGS::m_boardThickness
private

Board thickness for 3D viewer.

Definition at line 294 of file board_design_settings.h.

Referenced by BOARD_DESIGN_SETTINGS(), and GetBoardThickness().

◆ m_CopperEdgeClearance

◆ m_copperLayerCount

int BOARD_DESIGN_SETTINGS::m_copperLayerCount
private

Number of copper layers for this design.

Definition at line 288 of file board_design_settings.h.

Referenced by GetCopperLayerCount(), SetCopperLayerCount(), and SetEnabledLayers().

◆ m_currentNetClassName

wxString BOARD_DESIGN_SETTINGS::m_currentNetClassName
private

Current net class name used to display netclass info.

This is also the last used netclass after starting a track.

Definition at line 298 of file board_design_settings.h.

Referenced by GetCurrentMicroViaDrill(), GetCurrentMicroViaSize(), GetCurrentNetClassName(), and SetCurrentNetClass().

◆ m_CurrentViaType

VIATYPE BOARD_DESIGN_SETTINGS::m_CurrentViaType

(VIA_BLIND_BURIED, VIA_THROUGH, VIA_MICROVIA)

Definition at line 196 of file board_design_settings.h.

Referenced by BOARD_DESIGN_SETTINGS().

◆ m_customDiffPair

DIFF_PAIR_DIMENSION BOARD_DESIGN_SETTINGS::m_customDiffPair
private

Definition at line 286 of file board_design_settings.h.

Referenced by BOARD_DESIGN_SETTINGS().

◆ m_customTrackWidth

int BOARD_DESIGN_SETTINGS::m_customTrackWidth
private

◆ m_customViaSize

VIA_DIMENSION BOARD_DESIGN_SETTINGS::m_customViaSize
private

Definition at line 282 of file board_design_settings.h.

Referenced by BOARD_DESIGN_SETTINGS(), and GetCurrentViaDrill().

◆ m_DiffPairDimensionsList

◆ m_diffPairIndex

unsigned BOARD_DESIGN_SETTINGS::m_diffPairIndex
private

◆ m_DimensionPrecision

◆ m_DimensionUnits

◆ m_DRCSeverities

◆ m_enabledLayers

LSET BOARD_DESIGN_SETTINGS::m_enabledLayers
private

Bit-mask for layer enabling.

Definition at line 290 of file board_design_settings.h.

Referenced by BOARD_DESIGN_SETTINGS(), GetEnabledLayers(), SetCopperLayerCount(), SetEnabledLayers(), and SetVisibleLayers().

◆ m_GridOrigin

wxPoint BOARD_DESIGN_SETTINGS::m_GridOrigin

origin for grid offsets

Definition at line 258 of file board_design_settings.h.

Referenced by BOARD::GetGridOrigin(), LEGACY_PLUGIN::loadSETUP(), PCB_PARSER::parseSetup(), and BOARD::SetGridOrigin().

◆ m_HasStackup

bool BOARD_DESIGN_SETTINGS::m_HasStackup

Set to true if the board has a stackup management.

if m_hasStackup is false, a default basic stackup witll be used to generate the ;gbrjob file. if m_hasStackup is true, the stackup defined for the board is used. if not up to date, a error message will be set Could be removed later, or at least always set to true

Definition at line 270 of file board_design_settings.h.

Referenced by GERBER_JOBFILE_WRITER::addJSONMaterialStackup(), BOARD_DESIGN_SETTINGS(), PCB_IO::formatSetup(), and PANEL_SETUP_BOARD_STACKUP::TransferDataFromWindow().

◆ m_HoleToHoleMin

◆ m_LineThickness

◆ m_MaxError

◆ m_MicroViasAllowed

◆ m_MicroViasMinDrill

◆ m_MicroViasMinSize

◆ m_NetClasses

◆ m_Pad_Master

◆ m_RefDefaultlayer

◆ m_RefDefaultText

◆ m_RefDefaultVisibility

bool BOARD_DESIGN_SETTINGS::m_RefDefaultVisibility

◆ m_SolderMaskMargin

◆ m_SolderMaskMinWidth

◆ m_SolderPasteMargin

◆ m_SolderPasteMarginRatio

double BOARD_DESIGN_SETTINGS::m_SolderPasteMarginRatio

◆ m_stackup

BOARD_STACKUP BOARD_DESIGN_SETTINGS::m_stackup
private

the description of layers stackup, for board fabrication only physical layers are in layers stackup.

It includes not only layers enabled for the board edition, but also dielectic layers

Definition at line 304 of file board_design_settings.h.

Referenced by GetStackupDescriptor().

◆ m_TextItalic

◆ m_TextSize

◆ m_TextThickness

◆ m_TextUpright

◆ m_TrackMinWidth

◆ m_trackWidthIndex

unsigned BOARD_DESIGN_SETTINGS::m_trackWidthIndex
private

◆ m_TrackWidthList

◆ m_UseConnectedTrackWidth

◆ m_useCustomDiffPair

bool BOARD_DESIGN_SETTINGS::m_useCustomDiffPair
private

◆ m_useCustomTrackVia

bool BOARD_DESIGN_SETTINGS::m_useCustomTrackVia
private

◆ m_ValueDefaultlayer

◆ m_ValueDefaultText

◆ m_ValueDefaultVisibility

bool BOARD_DESIGN_SETTINGS::m_ValueDefaultVisibility

◆ m_ViasDimensionsList

◆ m_viaSizeIndex

unsigned BOARD_DESIGN_SETTINGS::m_viaSizeIndex
private

◆ m_ViasMinDrill

◆ m_ViasMinSize

◆ m_visibleElements

int BOARD_DESIGN_SETTINGS::m_visibleElements
private

Bit-mask for element category visibility.

Definition at line 293 of file board_design_settings.h.

Referenced by BOARD_DESIGN_SETTINGS(), GetVisibleElements(), SetElementVisibility(), and SetVisibleAlls().

◆ m_visibleLayers

LSET BOARD_DESIGN_SETTINGS::m_visibleLayers
private

Bit-mask for layer visibility.

Definition at line 291 of file board_design_settings.h.

Referenced by GetVisibleLayers(), SetEnabledLayers(), and SetLayerVisibility().

◆ m_ZoneUseNoOutlineInFill

bool BOARD_DESIGN_SETTINGS::m_ZoneUseNoOutlineInFill

Option to handle filled polygons in zones: the "legacy" option is using thick outlines around filled polygons: give the best shape the "new" option is using only filled polygons (no outline: give the faster redraw time moreover when exporting zone filled areas, the excatct shape is exported.

the legacy option can really create redraw time issues for large boards.true for new zone filling option

Definition at line 216 of file board_design_settings.h.

Referenced by BOARD_DESIGN_SETTINGS(), ZONE_FILLER::Fill(), PCB_IO::formatSetup(), PCB_PARSER::parseSetup(), PANEL_SETUP_FEATURE_CONSTRAINTS::TransferDataFromWindow(), and PANEL_SETUP_FEATURE_CONSTRAINTS::TransferDataToWindow().


The documentation for this class was generated from the following files: