KiCad PCB EDA Suite
board_design_settings.h
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24 
25 #ifndef BOARD_DESIGN_SETTINGS_H_
26 #define BOARD_DESIGN_SETTINGS_H_
27 
28 #include <class_pad.h>
29 #include <class_track.h>
30 #include <netclass.h>
31 #include <config_params.h>
33 
34 #define DEFAULT_SILK_LINE_WIDTH 0.12
35 #define DEFAULT_COPPER_LINE_WIDTH 0.20
36 #define DEFAULT_EDGE_WIDTH 0.05
37 #define DEFAULT_COURTYARD_WIDTH 0.05
38 #define DEFAULT_LINE_WIDTH 0.10
39 
40 #define DEFAULT_SILK_TEXT_SIZE 1.0
41 #define DEFAULT_COPPER_TEXT_SIZE 1.5
42 #define DEFAULT_TEXT_SIZE 1.0
43 
44 #define DEFAULT_SILK_TEXT_WIDTH 0.15
45 #define DEFAULT_COPPER_TEXT_WIDTH 0.30
46 #define DEFAULT_TEXT_WIDTH 0.15
47 
48 // Board thickness, mainly for 3D view:
49 #define DEFAULT_BOARD_THICKNESS_MM 1.6
50 
51 #define DEFAULT_PCB_EDGE_THICKNESS 0.15
52 
53 #define DEFAULT_SOLDERMASK_CLEARANCE 0.051 // soldermask to pad clearance
54 #define DEFAULT_SOLDERMASK_MIN_WIDTH 0.25 // soldermask minimum dam size
55 #define DEFAULT_SOLDERPASTE_CLEARANCE 0.0
56 #define DEFAULT_SOLDERPASTE_RATIO 0.0
57 
58 #define DEFAULT_CUSTOMTRACKWIDTH 0.2
59 #define DEFAULT_CUSTOMDPAIRWIDTH 0.125
60 #define DEFAULT_CUSTOMDPAIRGAP 0.18
61 #define DEFAULT_CUSTOMDPAIRVIAGAP 0.18
62 
63 #define DEFAULT_TRACKMINWIDTH 0.2 // track width min value
64 #define DEFAULT_VIASMINSIZE 0.4 // vias (not micro vias) min diameter
65 #define DEFAULT_VIASMINDRILL 0.3 // vias (not micro vias) min drill diameter
66 #define DEFAULT_MICROVIASMINSIZE 0.2 // micro vias (not vias) min diameter
67 #define DEFAULT_MICROVIASMINDRILL 0.1 // micro vias (not vias) min drill diameter
68 #define DEFAULT_HOLETOHOLEMIN 0.25 // separation between drilled hole edges
69 
70 #define DEFAULT_COPPEREDGECLEARANCE 0.01 // clearance between copper items and edge cuts
71 #define LEGACY_COPPEREDGECLEARANCE -0.01 // A flag to indicate the legacy method (based
72  // on edge cut line thicknesses) should be used.
73 
74 #define MINIMUM_ERROR_SIZE_MM 0.001
75 #define MAXIMUM_ERROR_SIZE_MM 0.1
76 
83 {
84  int m_Diameter; // <= 0 means use Netclass via diameter
85  int m_Drill; // <= 0 means use Netclass via drill
86 
88  {
89  m_Diameter = 0;
90  m_Drill = 0;
91  }
92 
93  VIA_DIMENSION( int aDiameter, int aDrill )
94  {
95  m_Diameter = aDiameter;
96  m_Drill = aDrill;
97  }
98 
99  bool operator==( const VIA_DIMENSION& aOther ) const
100  {
101  return ( m_Diameter == aOther.m_Diameter ) && ( m_Drill == aOther.m_Drill );
102  }
103 
104  bool operator<( const VIA_DIMENSION& aOther ) const
105  {
106  if( m_Diameter != aOther.m_Diameter )
107  return m_Diameter < aOther.m_Diameter;
108 
109  return m_Drill < aOther.m_Drill;
110  }
111 };
112 
113 
120 {
121  int m_Width; // <= 0 means use Netclass differential pair width
122  int m_Gap; // <= 0 means use Netclass differential pair gap
123  int m_ViaGap; // <= 0 means use Netclass differential pair via gap
124 
126  {
127  m_Width = 0;
128  m_Gap = 0;
129  m_ViaGap = 0;
130  }
131 
132  DIFF_PAIR_DIMENSION( int aWidth, int aGap, int aViaGap )
133  {
134  m_Width = aWidth;
135  m_Gap = aGap;
136  m_ViaGap = aViaGap;
137  }
138 
139  bool operator==( const DIFF_PAIR_DIMENSION& aOther ) const
140  {
141  return ( m_Width == aOther.m_Width )
142  && ( m_Gap == aOther.m_Gap )
143  && ( m_ViaGap == aOther.m_ViaGap );
144  }
145 
146  bool operator<( const DIFF_PAIR_DIMENSION& aOther ) const
147  {
148  if( m_Width != aOther.m_Width )
149  return m_Width < aOther.m_Width;
150 
151  if( m_Gap != aOther.m_Gap )
152  return m_Gap < aOther.m_Gap;
153 
154  return m_ViaGap < aOther.m_ViaGap;
155  }
156 };
157 
158 
159 enum
160 {
166 
168 };
169 
170 
176 {
177 public:
178  // Note: the first value in each dimensions list is the current netclass value
179  std::vector<int> m_TrackWidthList;
180  std::vector<VIA_DIMENSION> m_ViasDimensionsList;
181  std::vector<DIFF_PAIR_DIMENSION> m_DiffPairDimensionsList;
182 
183  // List of netclasses. There is always the default netclass.
185 
189 
192 
193  // if true, when creating a new track starting on an existing track, use this track width
201 
209 
210  // Maximum error allowed when approximating circles and arcs to segments
212 
213  // Global mask margins:
216  // 2 areas near than m_SolderMaskMinWidth
217  // are merged
220 
223 
224  // Arrays of default values for the various layer classes.
230 
233 
234  // Variables used in footprint editing (default value in item/footprint creation)
235 
236  wxString m_RefDefaultText;
237  // if empty, use footprint name as default
240  // should be a PCB_LAYER_ID, but use an int
241  // to save this param in config
242 
244  // if empty, use footprint name as default
247  // should be a PCB_LAYER_ID, but use an int
248  // to save this param in config
249 
250  // Miscellaneous
251  wxPoint m_AuxOrigin;
252  wxPoint m_GridOrigin;
253 
255  // when importing values or create a new pad
256 
265 
266 private:
267  // Indicies into the trackWidth, viaSizes and diffPairDimensions lists.
268  // The 0 index is always the current netclass value(s)
270  unsigned m_viaSizeIndex;
271  unsigned m_diffPairIndex;
272 
273  // Custom values for track/via sizes (specified via dialog instead of netclass or lists)
277 
278  // Custom values for differential pairs (specified via dialog instead of netclass/lists)
281 
283 
286 
289 
293 
299 
300 public:
302 
304 
309  inline NETCLASSPTR GetDefault() const
310  {
311  return m_NetClasses.GetDefault();
312  }
313 
318  inline const wxString& GetCurrentNetClassName() const
319  {
320  return m_currentNetClassName;
321  }
322 
327  inline bool UseNetClassTrack() const
328  {
329  return ( m_trackWidthIndex == 0 && !m_useCustomTrackVia );
330  }
331 
336  inline bool UseNetClassVia() const
337  {
338  return ( m_viaSizeIndex == 0 && !m_useCustomTrackVia );
339  }
340 
345  inline bool UseNetClassDiffPair() const
346  {
347  return ( m_diffPairIndex == 0 && !m_useCustomDiffPair );
348  }
349 
358  bool SetCurrentNetClass( const wxString& aNetClassName );
359 
365 
371 
378 
385 
390  inline unsigned GetTrackWidthIndex() const { return m_trackWidthIndex; }
391 
398  void SetTrackWidthIndex( unsigned aIndex );
399 
406  inline int GetCurrentTrackWidth() const
407  {
409  }
410 
418  inline void SetCustomTrackWidth( int aWidth )
419  {
420  m_customTrackWidth = aWidth;
421  }
422 
427  inline int GetCustomTrackWidth() const
428  {
429  return m_customTrackWidth;
430  }
431 
436  inline unsigned GetViaSizeIndex() const
437  {
438  return m_viaSizeIndex;
439  }
440 
447  void SetViaSizeIndex( unsigned aIndex );
448 
455  inline int GetCurrentViaSize() const
456  {
457  if( m_useCustomTrackVia )
459  else
460  return m_ViasDimensionsList[m_viaSizeIndex].m_Diameter;
461  }
462 
470  inline void SetCustomViaSize( int aSize )
471  {
472  m_customViaSize.m_Diameter = aSize;
473  }
474 
479  inline int GetCustomViaSize() const
480  {
482  }
483 
490  int GetCurrentViaDrill() const;
491 
499  inline void SetCustomViaDrill( int aDrill )
500  {
501  m_customViaSize.m_Drill = aDrill;
502  }
503 
508  inline int GetCustomViaDrill() const
509  {
510  return m_customViaSize.m_Drill;
511  }
512 
520  inline void UseCustomTrackViaSize( bool aEnabled )
521  {
522  m_useCustomTrackVia = aEnabled;
523  }
524 
529  inline bool UseCustomTrackViaSize() const
530  {
531  return m_useCustomTrackVia;
532  }
533 
538  inline unsigned GetDiffPairIndex() const { return m_diffPairIndex; }
539 
544  void SetDiffPairIndex( unsigned aIndex );
545 
552  inline void SetCustomDiffPairWidth( int aWidth )
553  {
554  m_customDiffPair.m_Width = aWidth;
555  }
556 
562  {
563  return m_customDiffPair.m_Width;
564  }
565 
572  inline void SetCustomDiffPairGap( int aGap )
573  {
574  m_customDiffPair.m_Gap = aGap;
575  }
576 
581  inline int GetCustomDiffPairGap()
582  {
583  return m_customDiffPair.m_Gap;
584  }
585 
592  inline void SetCustomDiffPairViaGap( int aGap )
593  {
594  m_customDiffPair.m_ViaGap = aGap;
595  }
596 
602  {
604  }
605 
611  inline void UseCustomDiffPairDimensions( bool aEnabled )
612  {
613  m_useCustomDiffPair = aEnabled;
614  }
615 
620  inline bool UseCustomDiffPairDimensions() const
621  {
622  return m_useCustomDiffPair;
623  }
624 
631  inline int GetCurrentDiffPairWidth() const
632  {
633  if( m_useCustomDiffPair )
634  return m_customDiffPair.m_Width;
635  else
637  }
638 
645  inline int GetCurrentDiffPairGap() const
646  {
647  if( m_useCustomDiffPair )
648  return m_customDiffPair.m_Gap;
649  else
651  }
652 
659  inline int GetCurrentDiffPairViaGap() const
660  {
661  if( m_useCustomDiffPair )
662  return m_customDiffPair.m_ViaGap;
663  else
664  return m_DiffPairDimensionsList[m_diffPairIndex].m_ViaGap;
665  }
666 
672  void SetMinHoleSeparation( int aDistance );
673 
678  void SetCopperEdgeClearance( int aDistance );
679 
684  void SetRequireCourtyardDefinitions( bool aRequire );
685 
690  void SetProhibitOverlappingCourtyards( bool aProhibit );
691 
697  inline LSET GetVisibleLayers() const
698  {
699  return m_visibleLayers;
700  }
701 
707  void SetVisibleAlls();
708 
714  inline void SetVisibleLayers( LSET aMask )
715  {
717  }
718 
725  inline bool IsLayerVisible( PCB_LAYER_ID aLayerId ) const
726  {
727  // If a layer is disabled, it is automatically invisible
728  return (m_visibleLayers & m_enabledLayers)[aLayerId];
729  }
730 
737  void SetLayerVisibility( PCB_LAYER_ID aLayerId, bool aNewState );
738 
744  inline int GetVisibleElements() const
745  {
746  return m_visibleElements;
747  }
748 
754  inline void SetVisibleElements( int aMask )
755  {
756  m_visibleElements = aMask;
757  }
758 
767  inline bool IsElementVisible( GAL_LAYER_ID aElementCategory ) const
768  {
769  return ( m_visibleElements & ( 1 << GAL_LAYER_INDEX( aElementCategory ) ) );
770  }
771 
779  void SetElementVisibility( GAL_LAYER_ID aElementCategory, bool aNewState );
780 
786  inline LSET GetEnabledLayers() const
787  {
788  return m_enabledLayers;
789  }
790 
796  void SetEnabledLayers( LSET aMask );
797 
804  inline bool IsLayerEnabled( PCB_LAYER_ID aLayerId ) const
805  {
806  return m_enabledLayers[aLayerId];
807  }
808 
813  inline int GetCopperLayerCount() const
814  {
815  return m_copperLayerCount;
816  }
817 
823  void SetCopperLayerCount( int aNewLayerCount );
824 
831  void AppendConfigs( BOARD* aBoard, PARAM_CFG_ARRAY* aResult );
832 
833  inline int GetBoardThickness() const { return m_boardThickness; }
834  inline void SetBoardThickness( int aThickness ) { m_boardThickness = aThickness; }
835 
840  int GetLineThickness( PCB_LAYER_ID aLayer ) const;
841 
846  wxSize GetTextSize( PCB_LAYER_ID aLayer ) const;
847 
852  int GetTextThickness( PCB_LAYER_ID aLayer ) const;
853 
854  bool GetTextItalic( PCB_LAYER_ID aLayer ) const;
855  bool GetTextUpright( PCB_LAYER_ID aLayer ) const;
856 
857  int GetLayerClass( PCB_LAYER_ID aLayer ) const;
858 
859 private:
860  void formatNetClass( NETCLASS* aNetClass, OUTPUTFORMATTER* aFormatter, int aNestLevel,
861  int aControlBits ) const;
862 };
863 
864 #endif // BOARD_DESIGN_SETTINGS_H_
bool IsElementVisible(GAL_LAYER_ID aElementCategory) const
Function IsElementVisible tests whether a given element category is visible.
int GetCurrentMicroViaSize()
Function GetCurrentMicroViaSize.
wxString m_RefDefaultText
Default ref text on fp creation.
int m_SolderMaskMargin
Solder mask margin.
bool UseNetClassTrack() const
Function UseNetClassTrack returns true if netclass values should be used to obtain appropriate track ...
void SetCopperLayerCount(int aNewLayerCount)
Function SetCopperLayerCount do what its name says...
Struct VIA_DIMENSION is a small helper container to handle a stock of specific vias each with unique ...
void SetEnabledLayers(LSET aMask)
Function SetEnabledLayers changes the bit-mask of enabled layers.
A list of parameters type.
void SetCopperEdgeClearance(int aDistance)
Function SetCopperEdgeClearance.
bool m_ValueDefaultVisibility
Default value text visibility on fp creation.
bool UseCustomDiffPairDimensions() const
Function UseCustomDiffPairDimensions.
void SetTrackWidthIndex(unsigned aIndex)
Function SetTrackWidthIndex sets the current track width list index to aIndex.
VIATYPE_T m_CurrentViaType
(VIA_BLIND_BURIED, VIA_THROUGH, VIA_MICROVIA)
int GetCustomViaSize() const
Function GetCustomViaSize.
wxString m_currentNetClassName
Current net class name used to display netclass info.
wxPoint m_GridOrigin
origin for grid offsets
int GetCurrentViaDrill() const
Function GetCurrentViaDrill.
int m_SolderPasteMargin
Solder paste margin absolute value.
int GetCurrentTrackWidth() const
Function GetCurrentTrackWidth.
this class manage the layers needed to make a physical board they are solder mask,...
void SetCustomDiffPairViaGap(int aGap)
Function SetCustomDiffPairViaGap Sets custom via gap for differential pairs (i.e.
void formatNetClass(NETCLASS *aNetClass, OUTPUTFORMATTER *aFormatter, int aNestLevel, int aControlBits) const
std::vector< int > m_TrackWidthList
int GetSmallestClearanceValue()
Function GetSmallestClearanceValue.
int GetBiggestClearanceValue()
Function GetBiggestClearanceValue.
bool IsLayerEnabled(PCB_LAYER_ID aLayerId) const
Function IsLayerEnabled tests whether a given layer is enabled.
BOARD_STACKUP m_stackup
the description of layers stackup, for board fabrication only physical layers are in layers stackup.
int GetCurrentDiffPairGap() const
Function GetCurrentDiffPairGap.
bool m_ProhibitOverlappingCourtyards
check for overlapping courtyards in DRC
int GetCurrentMicroViaDrill()
Function GetCurrentMicroViaDrill.
bool UseNetClassDiffPair() const
Function UseNetClassDiffPair returns true if netclass values should be used to obtain appropriate dif...
std::vector< DIFF_PAIR_DIMENSION > m_DiffPairDimensionsList
void SetCustomViaDrill(int aDrill)
Function SetCustomViaDrill Sets custom size for via drill (i.e.
void SetLayerVisibility(PCB_LAYER_ID aLayerId, bool aNewState)
Function SetLayerVisibility changes the visibility of a given layer.
void UseCustomDiffPairDimensions(bool aEnabled)
Function UseCustomDiffPairDimensions Enables/disables custom differential pair dimensions.
bool operator<(const VIA_DIMENSION &aOther) const
GAL_LAYER_ID
GAL layers are "virtual" layers, i.e.
bool IsLayerVisible(PCB_LAYER_ID aLayerId) const
Function IsLayerVisible tests whether a given layer is visible.
The common library.
bool operator<(const DIFF_PAIR_DIMENSION &aOther) const
Class OUTPUTFORMATTER is an important interface (abstract class) used to output 8 bit text in a conve...
Definition: richio.h:327
int m_ValueDefaultlayer
Default value text layer on fp creation.
void SetVisibleAlls()
Function SetVisibleAlls Set the bit-mask of all visible elements categories, including enabled layers...
DIFF_PAIR_DIMENSION m_customDiffPair
int GetTextThickness(PCB_LAYER_ID aLayer) const
Function GetTextThickness Returns the default text thickness from the layer class for the given layer...
VIATYPE_T
Definition: class_track.h:60
void SetBoardThickness(int aThickness)
Struct DIFF_PAIR_DIMENSION is a small helper container to handle a stock of specific differential pai...
void SetCustomViaSize(int aSize)
Function SetCustomViaSize Sets custom size for via diameter (i.e.
int GetCustomDiffPairWidth()
Function GetCustomDiffPairWidth.
Definitions for tracks, vias and zones.
int GetLayerClass(PCB_LAYER_ID aLayer) const
void SetVisibleLayers(LSET aMask)
Function SetVisibleLayers changes the bit-mask of visible layers.
bool GetTextUpright(PCB_LAYER_ID aLayer) const
bool GetTextItalic(PCB_LAYER_ID aLayer) const
int GetLineThickness(PCB_LAYER_ID aLayer) const
Function GetLineThickness Returns the default graphic segment thickness from the layer class for the ...
bool UseCustomTrackViaSize() const
Function UseCustomTrackViaSize.
int GetCustomViaDrill() const
Function GetCustomViaDrill.
wxSize m_TextSize[LAYER_CLASS_COUNT]
void SetViaSizeIndex(unsigned aIndex)
Function SetViaSizeIndex sets the current via size list index to aIndex.
BOARD_STACKUP & GetStackupDescriptor()
PCB_LAYER_ID
A quick note on layer IDs:
int m_HoleToHoleMin
Min width of peninsula between two drilled holes.
int m_TextThickness[LAYER_CLASS_COUNT]
Class LSET is a set of PCB_LAYER_IDs.
Class NETCLASSES is a container for NETCLASS instances.
Definition: netclass.h:224
#define GAL_LAYER_INDEX(x)
Use this macro to convert a GAL layer to a 0-indexed offset from LAYER_VIAS.
const wxString & GetCurrentNetClassName() const
Function GetCurrentNetClassName.
unsigned GetViaSizeIndex() const
Function GetViaSizeIndex.
void SetMinHoleSeparation(int aDistance)
Function SetMinHoleSeparation.
int m_TrackMinWidth
track min value for width ((min copper size value
bool UseNetClassVia() const
Function UseNetClassVia returns true if netclass values should be used to obtain appropriate via size...
void SetCustomDiffPairWidth(int aWidth)
Function SetCustomDiffPairWidth Sets custom track width for differential pairs (i....
int m_ViasMinSize
vias (not micro vias) min diameter
int GetCustomTrackWidth() const
Function GetCustomTrackWidth.
Class NETCLASS handles a collection of nets and the parameters used to route or test these nets.
Definition: netclass.h:55
int GetCurrentDiffPairWidth() const
Function GetCurrentDiffPairWidth.
unsigned GetTrackWidthIndex() const
Function GetTrackWidthIndex.
bool m_TextItalic[LAYER_CLASS_COUNT]
int m_ViasMinDrill
vias (not micro vias) min drill diameter
bool m_BlindBuriedViaAllowed
true to allow blind/buried vias
void SetDiffPairIndex(unsigned aIndex)
Function SetDiffPairIndex.
wxString m_ValueDefaultText
Default value text on fp creation.
void SetCustomDiffPairGap(int aGap)
Function SetCustomDiffPairGap Sets custom gap for differential pairs (i.e.
int m_MicroViasMinSize
micro vias (not vias) min diameter
int m_LineThickness[LAYER_CLASS_COUNT]
void AppendConfigs(BOARD *aBoard, PARAM_CFG_ARRAY *aResult)
Function AppendConfigs appends to aResult the configuration setting accessors which will later allow ...
void SetCustomTrackWidth(int aWidth)
Function SetCustomTrackWidth Sets custom width for track (i.e.
Pad object description.
LSET m_visibleLayers
Bit-mask for layer visibility.
bool operator==(const VIA_DIMENSION &aOther) const
int m_visibleElements
Bit-mask for element category visibility.
bool m_RequireCourtyards
require courtyard definitions in footprints
int GetCurrentViaSize() const
Function GetCurrentViaSize.
LSET GetVisibleLayers() const
Function GetVisibleLayers returns a bit-mask of all the layers that are visible.
bool SetCurrentNetClass(const wxString &aNetClassName)
Function SetCurrentNetClass Must be called after a netclass selection (or after a netclass parameter ...
int GetVisibleElements() const
Function GetVisibleElements returns a bit-mask of all the element categories that are visible.
NETCLASSPTR GetDefault() const
Function GetDefault.
Class BOARD holds information pertinent to a Pcbnew printed circuit board.
Definition: class_board.h:161
LSET GetEnabledLayers() const
Function GetEnabledLayers returns a bit-mask of all the layers that are enabled.
int GetCustomDiffPairViaGap()
Function GetCustomDiffPairViaGap.
void SetProhibitOverlappingCourtyards(bool aProhibit)
Function SetProhibitOverlappingCourtyards.
bool m_ZoneUseNoOutlineInFill
Option to handle filled polygons in zones: the "legacy" option is using thick outlines around filled ...
D_PAD m_Pad_Master
A dummy pad to store all default parameters.
void SetVisibleElements(int aMask)
Function SetVisibleElements changes the bit-mask of visible element categories.
int GetCurrentDiffPairViaGap() const
Function GetCurrentDiffPairViaGap.
int m_RefDefaultlayer
Default ref text layer on fp creation.
void SetElementVisibility(GAL_LAYER_ID aElementCategory, bool aNewState)
Function SetElementVisibility changes the visibility of an element category.
std::vector< VIA_DIMENSION > m_ViasDimensionsList
DIFF_PAIR_DIMENSION(int aWidth, int aGap, int aViaGap)
NETCLASSPTR GetDefault() const
Function GetDefault.
Definition: netclass.h:268
bool operator==(const DIFF_PAIR_DIMENSION &aOther) const
VIA_DIMENSION(int aDiameter, int aDrill)
unsigned GetDiffPairIndex() const
Function GetDiffPairIndex.
int m_copperLayerCount
Number of copper layers for this design.
bool m_MicroViasAllowed
true to allow micro vias
void SetRequireCourtyardDefinitions(bool aRequire)
Function SetRequireCourtyardDefinitions.
bool m_HasStackup
Set to true if the board has a stackup management.
int m_MicroViasMinDrill
micro vias (not vias) min drill diameter
double m_SolderPasteMarginRatio
Solder pask margin ratio value of pad size The final margin is the sum of these 2 values.
int GetCopperLayerCount() const
Function GetCopperLayerCount.
LSET m_enabledLayers
Bit-mask for layer enabling.
bool m_RefDefaultVisibility
Default ref text visibility on fp creation.
wxPoint m_AuxOrigin
origin for plot exports
wxSize GetTextSize(PCB_LAYER_ID aLayer) const
Function GetTextSize Returns the default text size from the layer class for the given layer.
int m_boardThickness
Board thickness for 3D viewer.
int GetCustomDiffPairGap()
Function GetCustomDiffPairGap.
bool m_TextUpright[LAYER_CLASS_COUNT]
void UseCustomTrackViaSize(bool aEnabled)
Function UseCustomTrackViaSize Enables/disables custom track/via size settings.
int m_SolderMaskMinWidth
Solder mask min width.
Class BOARD_DESIGN_SETTINGS contains design settings for a BOARD object.