KiCad PCB EDA Suite
board_design_settings.h
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2  * This program source code file is part of KiCad, a free EDA CAD application.
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24 
25 #ifndef BOARD_DESIGN_SETTINGS_H_
26 #define BOARD_DESIGN_SETTINGS_H_
27 
28 #include <class_pad.h>
29 #include <netclass.h>
30 #include <config_params.h>
32 
33 #define DEFAULT_SILK_LINE_WIDTH 0.12
34 #define DEFAULT_COPPER_LINE_WIDTH 0.20
35 #define DEFAULT_EDGE_WIDTH 0.05
36 #define DEFAULT_COURTYARD_WIDTH 0.05
37 #define DEFAULT_LINE_WIDTH 0.10
38 
39 #define DEFAULT_SILK_TEXT_SIZE 1.0
40 #define DEFAULT_COPPER_TEXT_SIZE 1.5
41 #define DEFAULT_TEXT_SIZE 1.0
42 
43 #define DEFAULT_SILK_TEXT_WIDTH 0.15
44 #define DEFAULT_COPPER_TEXT_WIDTH 0.30
45 #define DEFAULT_TEXT_WIDTH 0.15
46 
47 // Board thickness, mainly for 3D view:
48 #define DEFAULT_BOARD_THICKNESS_MM 1.6
49 
50 #define DEFAULT_PCB_EDGE_THICKNESS 0.15
51 
52 #define DEFAULT_SOLDERMASK_CLEARANCE 0.05 // soldermask to pad clearance
53 
54 // DEFAULT_SOLDERMASK_MIN_WIDTH is only used in Gerber files: soldermask minimum size.
55 // Set to 0, because using non 0 value creates an annoying issue in Gerber files:
56 // pads are no longer identified as pads (Flashed items or regions)
57 // Therefore solder mask min width must be used only in specific cases
58 // for instance for home made boards
59 #define DEFAULT_SOLDERMASK_MIN_WIDTH 0.0
60 
61 #define DEFAULT_SOLDERPASTE_CLEARANCE 0.0
62 #define DEFAULT_SOLDERPASTE_RATIO 0.0
63 
64 #define DEFAULT_CUSTOMTRACKWIDTH 0.2
65 #define DEFAULT_CUSTOMDPAIRWIDTH 0.125
66 #define DEFAULT_CUSTOMDPAIRGAP 0.18
67 #define DEFAULT_CUSTOMDPAIRVIAGAP 0.18
68 
69 #define DEFAULT_TRACKMINWIDTH 0.2 // track width min value
70 #define DEFAULT_VIASMINSIZE 0.4 // vias (not micro vias) min diameter
71 #define DEFAULT_VIASMINDRILL 0.3 // vias (not micro vias) min drill diameter
72 #define DEFAULT_MICROVIASMINSIZE 0.2 // micro vias (not vias) min diameter
73 #define DEFAULT_MICROVIASMINDRILL 0.1 // micro vias (not vias) min drill diameter
74 #define DEFAULT_HOLETOHOLEMIN 0.25 // separation between drilled hole edges
75 
76 #define DEFAULT_COPPEREDGECLEARANCE 0.01 // clearance between copper items and edge cuts
77 #define LEGACY_COPPEREDGECLEARANCE -0.01 // A flag to indicate the legacy method (based
78  // on edge cut line thicknesses) should be used.
79 
80 #define MINIMUM_ERROR_SIZE_MM 0.001
81 #define MAXIMUM_ERROR_SIZE_MM 0.1
82 
89 {
90  int m_Diameter; // <= 0 means use Netclass via diameter
91  int m_Drill; // <= 0 means use Netclass via drill
92 
94  {
95  m_Diameter = 0;
96  m_Drill = 0;
97  }
98 
99  VIA_DIMENSION( int aDiameter, int aDrill )
100  {
101  m_Diameter = aDiameter;
102  m_Drill = aDrill;
103  }
104 
105  bool operator==( const VIA_DIMENSION& aOther ) const
106  {
107  return ( m_Diameter == aOther.m_Diameter ) && ( m_Drill == aOther.m_Drill );
108  }
109 
110  bool operator<( const VIA_DIMENSION& aOther ) const
111  {
112  if( m_Diameter != aOther.m_Diameter )
113  return m_Diameter < aOther.m_Diameter;
114 
115  return m_Drill < aOther.m_Drill;
116  }
117 };
118 
119 
126 {
127  int m_Width; // <= 0 means use Netclass differential pair width
128  int m_Gap; // <= 0 means use Netclass differential pair gap
129  int m_ViaGap; // <= 0 means use Netclass differential pair via gap
130 
132  {
133  m_Width = 0;
134  m_Gap = 0;
135  m_ViaGap = 0;
136  }
137 
138  DIFF_PAIR_DIMENSION( int aWidth, int aGap, int aViaGap )
139  {
140  m_Width = aWidth;
141  m_Gap = aGap;
142  m_ViaGap = aViaGap;
143  }
144 
145  bool operator==( const DIFF_PAIR_DIMENSION& aOther ) const
146  {
147  return ( m_Width == aOther.m_Width )
148  && ( m_Gap == aOther.m_Gap )
149  && ( m_ViaGap == aOther.m_ViaGap );
150  }
151 
152  bool operator<( const DIFF_PAIR_DIMENSION& aOther ) const
153  {
154  if( m_Width != aOther.m_Width )
155  return m_Width < aOther.m_Width;
156 
157  if( m_Gap != aOther.m_Gap )
158  return m_Gap < aOther.m_Gap;
159 
160  return m_ViaGap < aOther.m_ViaGap;
161  }
162 };
163 
164 
165 enum
166 {
172 
174 };
175 
176 // forward declaration from class_track.h
177 enum class VIATYPE : int;
178 
184 {
185 public:
186  // Note: the first value in each dimensions list is the current netclass value
187  std::vector<int> m_TrackWidthList;
188  std::vector<VIA_DIMENSION> m_ViasDimensionsList;
189  std::vector<DIFF_PAIR_DIMENSION> m_DiffPairDimensionsList;
190 
191  // List of netclasses. There is always the default netclass.
193 
197 
198  bool m_UseConnectedTrackWidth; // use width of existing track when creating a new,
199  // connected track
200  int m_TrackMinWidth; // track min value for width ((min copper size value
201  int m_ViasMinSize; // vias (not micro vias) min diameter
202  int m_ViasMinDrill; // vias (not micro vias) min drill diameter
203  int m_MicroViasMinSize; // micro vias min diameter
204  int m_MicroViasMinDrill; // micro vias min drill diameter
206  int m_HoleToHoleMin; // Min width of peninsula between two drilled holes
207 
208  std::map< int, int > m_DRCSeverities; // Map from DRCErrorCode to SEVERITY
209 
217 
218  // Maximum error allowed when approximating circles and arcs to segments
220 
221  // Global mask margins:
224  // 2 areas near than m_SolderMaskMinWidth
225  // are merged
228 
230  // Arrays of default values for the various layer classes.
231  int m_LineThickness[ LAYER_CLASS_COUNT ];
232  wxSize m_TextSize[ LAYER_CLASS_COUNT ];
233  int m_TextThickness[ LAYER_CLASS_COUNT ];
234  bool m_TextItalic[ LAYER_CLASS_COUNT ];
235  bool m_TextUpright[ LAYER_CLASS_COUNT ];
236 
239 
240  // Variables used in footprint editing (default value in item/footprint creation)
241 
242  wxString m_RefDefaultText;
243  // if empty, use footprint name as default
246  // should be a PCB_LAYER_ID, but use an int
247  // to save this param in config
248 
250  // if empty, use footprint name as default
253  // should be a PCB_LAYER_ID, but use an int
254  // to save this param in config
255 
256  // Miscellaneous
259 
261  // when importing values or create a new pad
262 
271 
272 private:
273  // Indicies into the trackWidth, viaSizes and diffPairDimensions lists.
274  // The 0 index is always the current netclass value(s)
276  unsigned m_viaSizeIndex;
277  unsigned m_diffPairIndex;
278 
279  // Custom values for track/via sizes (specified via dialog instead of netclass or lists)
283 
284  // Custom values for differential pairs (specified via dialog instead of netclass/lists)
287 
289 
292 
295 
299 
305 
306 public:
308 
310 
311  int GetSeverity( int aDRCErrorCode );
312 
316  bool Ignore( int aDRCErrorCode );
317 
322  inline NETCLASSPTR GetDefault() const
323  {
324  return m_NetClasses.GetDefault();
325  }
326 
331  inline const wxString& GetCurrentNetClassName() const
332  {
333  return m_currentNetClassName;
334  }
335 
340  inline bool UseNetClassTrack() const
341  {
342  return ( m_trackWidthIndex == 0 && !m_useCustomTrackVia );
343  }
344 
349  inline bool UseNetClassVia() const
350  {
351  return ( m_viaSizeIndex == 0 && !m_useCustomTrackVia );
352  }
353 
358  inline bool UseNetClassDiffPair() const
359  {
360  return ( m_diffPairIndex == 0 && !m_useCustomDiffPair );
361  }
362 
371  bool SetCurrentNetClass( const wxString& aNetClassName );
372 
378 
384 
391 
398 
403  inline unsigned GetTrackWidthIndex() const { return m_trackWidthIndex; }
404 
411  void SetTrackWidthIndex( unsigned aIndex );
412 
419  inline int GetCurrentTrackWidth() const
420  {
421  return m_useCustomTrackVia ? m_customTrackWidth : m_TrackWidthList[m_trackWidthIndex];
422  }
423 
431  inline void SetCustomTrackWidth( int aWidth )
432  {
433  m_customTrackWidth = aWidth;
434  }
435 
440  inline int GetCustomTrackWidth() const
441  {
442  return m_customTrackWidth;
443  }
444 
449  inline unsigned GetViaSizeIndex() const
450  {
451  return m_viaSizeIndex;
452  }
453 
460  void SetViaSizeIndex( unsigned aIndex );
461 
468  inline int GetCurrentViaSize() const
469  {
470  if( m_useCustomTrackVia )
471  return m_customViaSize.m_Diameter;
472  else
473  return m_ViasDimensionsList[m_viaSizeIndex].m_Diameter;
474  }
475 
483  inline void SetCustomViaSize( int aSize )
484  {
485  m_customViaSize.m_Diameter = aSize;
486  }
487 
492  inline int GetCustomViaSize() const
493  {
494  return m_customViaSize.m_Diameter;
495  }
496 
503  int GetCurrentViaDrill() const;
504 
512  inline void SetCustomViaDrill( int aDrill )
513  {
514  m_customViaSize.m_Drill = aDrill;
515  }
516 
521  inline int GetCustomViaDrill() const
522  {
523  return m_customViaSize.m_Drill;
524  }
525 
533  inline void UseCustomTrackViaSize( bool aEnabled )
534  {
535  m_useCustomTrackVia = aEnabled;
536  }
537 
542  inline bool UseCustomTrackViaSize() const
543  {
544  return m_useCustomTrackVia;
545  }
546 
551  inline unsigned GetDiffPairIndex() const { return m_diffPairIndex; }
552 
557  void SetDiffPairIndex( unsigned aIndex );
558 
565  inline void SetCustomDiffPairWidth( int aWidth )
566  {
567  m_customDiffPair.m_Width = aWidth;
568  }
569 
575  {
576  return m_customDiffPair.m_Width;
577  }
578 
585  inline void SetCustomDiffPairGap( int aGap )
586  {
587  m_customDiffPair.m_Gap = aGap;
588  }
589 
594  inline int GetCustomDiffPairGap()
595  {
596  return m_customDiffPair.m_Gap;
597  }
598 
605  inline void SetCustomDiffPairViaGap( int aGap )
606  {
607  m_customDiffPair.m_ViaGap = aGap;
608  }
609 
615  {
616  return m_customDiffPair.m_ViaGap > 0 ? m_customDiffPair.m_ViaGap : m_customDiffPair.m_Gap;
617  }
618 
624  inline void UseCustomDiffPairDimensions( bool aEnabled )
625  {
626  m_useCustomDiffPair = aEnabled;
627  }
628 
633  inline bool UseCustomDiffPairDimensions() const
634  {
635  return m_useCustomDiffPair;
636  }
637 
644  inline int GetCurrentDiffPairWidth() const
645  {
646  if( m_useCustomDiffPair )
647  return m_customDiffPair.m_Width;
648  else
649  return m_DiffPairDimensionsList[m_diffPairIndex].m_Width;
650  }
651 
658  inline int GetCurrentDiffPairGap() const
659  {
660  if( m_useCustomDiffPair )
661  return m_customDiffPair.m_Gap;
662  else
663  return m_DiffPairDimensionsList[m_diffPairIndex].m_Gap;
664  }
665 
672  inline int GetCurrentDiffPairViaGap() const
673  {
674  if( m_useCustomDiffPair )
675  return m_customDiffPair.m_ViaGap;
676  else
677  return m_DiffPairDimensionsList[m_diffPairIndex].m_ViaGap;
678  }
679 
685  void SetMinHoleSeparation( int aDistance );
686 
691  void SetCopperEdgeClearance( int aDistance );
692 
698  inline LSET GetVisibleLayers() const
699  {
700  return m_visibleLayers;
701  }
702 
708  void SetVisibleAlls();
709 
715  inline void SetVisibleLayers( LSET aMask )
716  {
717  m_visibleLayers = aMask & m_enabledLayers;
718  }
719 
726  inline bool IsLayerVisible( PCB_LAYER_ID aLayerId ) const
727  {
728  // If a layer is disabled, it is automatically invisible
729  return (m_visibleLayers & m_enabledLayers)[aLayerId];
730  }
731 
738  void SetLayerVisibility( PCB_LAYER_ID aLayerId, bool aNewState );
739 
745  inline int GetVisibleElements() const
746  {
747  return m_visibleElements;
748  }
749 
755  inline void SetVisibleElements( int aMask )
756  {
757  m_visibleElements = aMask;
758  }
759 
768  inline bool IsElementVisible( GAL_LAYER_ID aElementCategory ) const
769  {
770  return ( m_visibleElements & ( 1 << GAL_LAYER_INDEX( aElementCategory ) ) );
771  }
772 
780  void SetElementVisibility( GAL_LAYER_ID aElementCategory, bool aNewState );
781 
787  inline LSET GetEnabledLayers() const
788  {
789  return m_enabledLayers;
790  }
791 
797  void SetEnabledLayers( LSET aMask );
798 
805  inline bool IsLayerEnabled( PCB_LAYER_ID aLayerId ) const
806  {
807  return m_enabledLayers[aLayerId];
808  }
809 
814  inline int GetCopperLayerCount() const
815  {
816  return m_copperLayerCount;
817  }
818 
824  void SetCopperLayerCount( int aNewLayerCount );
825 
832  void AppendConfigs( BOARD* aBoard, std::vector<PARAM_CFG*>* aResult );
833 
834  inline int GetBoardThickness() const { return m_boardThickness; }
835  inline void SetBoardThickness( int aThickness ) { m_boardThickness = aThickness; }
836 
841  int GetLineThickness( PCB_LAYER_ID aLayer ) const;
842 
847  wxSize GetTextSize( PCB_LAYER_ID aLayer ) const;
848 
853  int GetTextThickness( PCB_LAYER_ID aLayer ) const;
854 
855  bool GetTextItalic( PCB_LAYER_ID aLayer ) const;
856  bool GetTextUpright( PCB_LAYER_ID aLayer ) const;
857 
858  int GetLayerClass( PCB_LAYER_ID aLayer ) const;
859 
860 private:
861  void formatNetClass( NETCLASS* aNetClass, OUTPUTFORMATTER* aFormatter, int aNestLevel,
862  int aControlBits ) const;
863 };
864 
865 #endif // BOARD_DESIGN_SETTINGS_H_
bool IsElementVisible(GAL_LAYER_ID aElementCategory) const
Function IsElementVisible tests whether a given element category is visible.
int GetCurrentMicroViaSize()
Function GetCurrentMicroViaSize.
wxString m_RefDefaultText
Default ref text on fp creation.
int m_SolderMaskMargin
Solder mask margin.
bool UseNetClassTrack() const
Function UseNetClassTrack returns true if netclass values should be used to obtain appropriate track ...
void SetCopperLayerCount(int aNewLayerCount)
Function SetCopperLayerCount do what its name says...
Struct VIA_DIMENSION is a small helper container to handle a stock of specific vias each with unique ...
void SetEnabledLayers(LSET aMask)
Function SetEnabledLayers changes the bit-mask of enabled layers.
void SetCopperEdgeClearance(int aDistance)
Function SetCopperEdgeClearance.
bool m_ValueDefaultVisibility
Default value text visibility on fp creation.
bool UseCustomDiffPairDimensions() const
Function UseCustomDiffPairDimensions.
void SetTrackWidthIndex(unsigned aIndex)
Function SetTrackWidthIndex sets the current track width list index to aIndex.
int GetCustomViaSize() const
Function GetCustomViaSize.
wxString m_currentNetClassName
Current net class name used to display netclass info.
wxPoint m_GridOrigin
origin for grid offsets
int GetCurrentViaDrill() const
Function GetCurrentViaDrill.
int m_SolderPasteMargin
Solder paste margin absolute value.
int GetCurrentTrackWidth() const
Function GetCurrentTrackWidth.
this class manage the layers needed to make a physical board they are solder mask,...
void SetCustomDiffPairViaGap(int aGap)
Function SetCustomDiffPairViaGap Sets custom via gap for differential pairs (i.e.
void formatNetClass(NETCLASS *aNetClass, OUTPUTFORMATTER *aFormatter, int aNestLevel, int aControlBits) const
std::vector< int > m_TrackWidthList
int GetSmallestClearanceValue()
Function GetSmallestClearanceValue.
int GetBiggestClearanceValue()
Function GetBiggestClearanceValue.
bool IsLayerEnabled(PCB_LAYER_ID aLayerId) const
Function IsLayerEnabled tests whether a given layer is enabled.
BOARD_STACKUP m_stackup
the description of layers stackup, for board fabrication only physical layers are in layers stackup.
int GetCurrentDiffPairGap() const
Function GetCurrentDiffPairGap.
int GetCurrentMicroViaDrill()
Function GetCurrentMicroViaDrill.
bool UseNetClassDiffPair() const
Function UseNetClassDiffPair returns true if netclass values should be used to obtain appropriate dif...
std::vector< DIFF_PAIR_DIMENSION > m_DiffPairDimensionsList
std::map< int, int > m_DRCSeverities
void SetCustomViaDrill(int aDrill)
Function SetCustomViaDrill Sets custom size for via drill (i.e.
void SetLayerVisibility(PCB_LAYER_ID aLayerId, bool aNewState)
Function SetLayerVisibility changes the visibility of a given layer.
bool Ignore(int aDRCErrorCode)
returns true if the DRC error code's severity is SEVERITY_IGNORE
void UseCustomDiffPairDimensions(bool aEnabled)
Function UseCustomDiffPairDimensions Enables/disables custom differential pair dimensions.
bool operator<(const VIA_DIMENSION &aOther) const
GAL_LAYER_ID
GAL layers are "virtual" layers, i.e.
bool IsLayerVisible(PCB_LAYER_ID aLayerId) const
Function IsLayerVisible tests whether a given layer is visible.
bool operator<(const DIFF_PAIR_DIMENSION &aOther) const
OUTPUTFORMATTER is an important interface (abstract class) used to output 8 bit text in a convenient ...
Definition: richio.h:327
int m_ValueDefaultlayer
Default value text layer on fp creation.
void SetVisibleAlls()
Function SetVisibleAlls Set the bit-mask of all visible elements categories, including enabled layers...
DIFF_PAIR_DIMENSION m_customDiffPair
int GetTextThickness(PCB_LAYER_ID aLayer) const
Function GetTextThickness Returns the default text thickness from the layer class for the given layer...
void SetBoardThickness(int aThickness)
VIATYPE m_CurrentViaType
(VIA_BLIND_BURIED, VIA_THROUGH, VIA_MICROVIA)
Struct DIFF_PAIR_DIMENSION is a small helper container to handle a stock of specific differential pai...
void SetCustomViaSize(int aSize)
Function SetCustomViaSize Sets custom size for via diameter (i.e.
int GetCustomDiffPairWidth()
Function GetCustomDiffPairWidth.
int GetLayerClass(PCB_LAYER_ID aLayer) const
void SetVisibleLayers(LSET aMask)
Function SetVisibleLayers changes the bit-mask of visible layers.
bool GetTextUpright(PCB_LAYER_ID aLayer) const
bool GetTextItalic(PCB_LAYER_ID aLayer) const
int GetLineThickness(PCB_LAYER_ID aLayer) const
Function GetLineThickness Returns the default graphic segment thickness from the layer class for the ...
bool UseCustomTrackViaSize() const
Function UseCustomTrackViaSize.
int GetCustomViaDrill() const
Function GetCustomViaDrill.
void SetViaSizeIndex(unsigned aIndex)
Function SetViaSizeIndex sets the current via size list index to aIndex.
BOARD_STACKUP & GetStackupDescriptor()
PCB_LAYER_ID
A quick note on layer IDs:
LSET is a set of PCB_LAYER_IDs.
NETCLASSES is a container for NETCLASS instances.
Definition: netclass.h:224
#define GAL_LAYER_INDEX(x)
Use this macro to convert a GAL layer to a 0-indexed offset from LAYER_VIAS.
const wxString & GetCurrentNetClassName() const
Function GetCurrentNetClassName.
unsigned GetViaSizeIndex() const
Function GetViaSizeIndex.
void SetMinHoleSeparation(int aDistance)
Function SetMinHoleSeparation.
bool UseNetClassVia() const
Function UseNetClassVia returns true if netclass values should be used to obtain appropriate via size...
void SetCustomDiffPairWidth(int aWidth)
Function SetCustomDiffPairWidth Sets custom track width for differential pairs (i....
int GetCustomTrackWidth() const
Function GetCustomTrackWidth.
NETCLASS handles a collection of nets and the parameters used to route or test these nets.
Definition: netclass.h:55
VIATYPE
Definition: class_track.h:62
int GetCurrentDiffPairWidth() const
Function GetCurrentDiffPairWidth.
unsigned GetTrackWidthIndex() const
Function GetTrackWidthIndex.
bool m_BlindBuriedViaAllowed
true to allow blind/buried vias
void SetDiffPairIndex(unsigned aIndex)
Function SetDiffPairIndex.
wxString m_ValueDefaultText
Default value text on fp creation.
void SetCustomDiffPairGap(int aGap)
Function SetCustomDiffPairGap Sets custom gap for differential pairs (i.e.
void SetCustomTrackWidth(int aWidth)
Function SetCustomTrackWidth Sets custom width for track (i.e.
Pad object description.
LSET m_visibleLayers
Bit-mask for layer visibility.
bool operator==(const VIA_DIMENSION &aOther) const
int m_visibleElements
Bit-mask for element category visibility.
int GetCurrentViaSize() const
Function GetCurrentViaSize.
LSET GetVisibleLayers() const
Function GetVisibleLayers returns a bit-mask of all the layers that are visible.
bool SetCurrentNetClass(const wxString &aNetClassName)
Function SetCurrentNetClass Must be called after a netclass selection (or after a netclass parameter ...
int GetVisibleElements() const
Function GetVisibleElements returns a bit-mask of all the element categories that are visible.
NETCLASSPTR GetDefault() const
Function GetDefault.
BOARD holds information pertinent to a Pcbnew printed circuit board.
Definition: class_board.h:163
LSET GetEnabledLayers() const
Function GetEnabledLayers returns a bit-mask of all the layers that are enabled.
int GetCustomDiffPairViaGap()
Function GetCustomDiffPairViaGap.
bool m_ZoneUseNoOutlineInFill
Option to handle filled polygons in zones: the "legacy" option is using thick outlines around filled ...
D_PAD m_Pad_Master
A dummy pad to store all default parameters.
void SetVisibleElements(int aMask)
Function SetVisibleElements changes the bit-mask of visible element categories.
int GetCurrentDiffPairViaGap() const
Function GetCurrentDiffPairViaGap.
int m_RefDefaultlayer
Default ref text layer on fp creation.
void SetElementVisibility(GAL_LAYER_ID aElementCategory, bool aNewState)
Function SetElementVisibility changes the visibility of an element category.
std::vector< VIA_DIMENSION > m_ViasDimensionsList
DIFF_PAIR_DIMENSION(int aWidth, int aGap, int aViaGap)
NETCLASSPTR GetDefault() const
Function GetDefault.
Definition: netclass.h:268
bool operator==(const DIFF_PAIR_DIMENSION &aOther) const
VIA_DIMENSION(int aDiameter, int aDrill)
unsigned GetDiffPairIndex() const
Function GetDiffPairIndex.
int m_copperLayerCount
Number of copper layers for this design.
bool m_MicroViasAllowed
true to allow micro vias
bool m_HasStackup
Set to true if the board has a stackup management.
double m_SolderPasteMarginRatio
Solder pask margin ratio value of pad size The final margin is the sum of these 2 values.
int GetSeverity(int aDRCErrorCode)
int GetCopperLayerCount() const
Function GetCopperLayerCount.
LSET m_enabledLayers
Bit-mask for layer enabling.
bool m_RefDefaultVisibility
Default ref text visibility on fp creation.
wxPoint m_AuxOrigin
origin for plot exports
wxSize GetTextSize(PCB_LAYER_ID aLayer) const
Function GetTextSize Returns the default text size from the layer class for the given layer.
int m_boardThickness
Board thickness for 3D viewer.
int GetCustomDiffPairGap()
Function GetCustomDiffPairGap.
void UseCustomTrackViaSize(bool aEnabled)
Function UseCustomTrackViaSize Enables/disables custom track/via size settings.
int m_SolderMaskMinWidth
Solder mask min width.
void AppendConfigs(BOARD *aBoard, std::vector< PARAM_CFG * > *aResult)
Function AppendConfigs appends to aResult the configuration setting accessors which will later allow ...
BOARD_DESIGN_SETTINGS contains design settings for a BOARD object.