KiCad PCB EDA Suite
board_design_settings.h
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24 
25 #ifndef BOARD_DESIGN_SETTINGS_H_
26 #define BOARD_DESIGN_SETTINGS_H_
27 
28 #include <class_pad.h>
29 #include <netclass.h>
30 #include <config_params.h>
32 #include <drc/drc_rule.h>
34 #include <widgets/ui_common.h>
35 #include <zone_settings.h>
36 
37 
38 #define DEFAULT_SILK_LINE_WIDTH 0.12
39 #define DEFAULT_COPPER_LINE_WIDTH 0.20
40 #define DEFAULT_EDGE_WIDTH 0.05
41 #define DEFAULT_COURTYARD_WIDTH 0.05
42 #define DEFAULT_LINE_WIDTH 0.10
43 
44 #define DEFAULT_SILK_TEXT_SIZE 1.0
45 #define DEFAULT_COPPER_TEXT_SIZE 1.5
46 #define DEFAULT_TEXT_SIZE 1.0
47 
48 #define DEFAULT_SILK_TEXT_WIDTH 0.15
49 #define DEFAULT_COPPER_TEXT_WIDTH 0.30
50 #define DEFAULT_TEXT_WIDTH 0.15
51 
52 // Board thickness, mainly for 3D view:
53 #define DEFAULT_BOARD_THICKNESS_MM 1.6
54 
55 #define DEFAULT_PCB_EDGE_THICKNESS 0.15
56 
57 // soldermask to pad clearance. The default is 0 because usually board houses
58 // create a clearance depending on their fab process:
59 // mask material, color, price ...
60 #define DEFAULT_SOLDERMASK_CLEARANCE 0.0
61 
62 // DEFAULT_SOLDERMASK_MIN_WIDTH is only used in Gerber files: soldermask minimum size.
63 // Set to 0, because using non 0 value creates an annoying issue in Gerber files:
64 // pads are no longer identified as pads (Flashed items or regions)
65 // Therefore solder mask min width must be used only in specific cases
66 // for instance for home made boards
67 #define DEFAULT_SOLDERMASK_MIN_WIDTH 0.0
68 
69 #define DEFAULT_SOLDERPASTE_CLEARANCE 0.0
70 #define DEFAULT_SOLDERPASTE_RATIO 0.0
71 
72 #define DEFAULT_CUSTOMTRACKWIDTH 0.2
73 #define DEFAULT_CUSTOMDPAIRWIDTH 0.125
74 #define DEFAULT_CUSTOMDPAIRGAP 0.18
75 #define DEFAULT_CUSTOMDPAIRVIAGAP 0.18
76 
77 #define DEFAULT_MINCLEARANCE 0.0 // overall min clearance
78 #define DEFAULT_TRACKMINWIDTH 0.2 // track width min value
79 #define DEFAULT_VIASMINSIZE 0.4 // vias (not micro vias) min diameter
80 #define DEFAULT_MINTHROUGHDRILL 0.3 // through holes (not micro vias) min drill diameter
81 #define DEFAULT_MICROVIASMINSIZE 0.2 // micro vias (not vias) min diameter
82 #define DEFAULT_MICROVIASMINDRILL 0.1 // micro vias (not vias) min drill diameter
83 #define DEFAULT_HOLETOHOLEMIN 0.25 // separation between drilled hole edges
84 
85 #define DEFAULT_COPPEREDGECLEARANCE 0.01 // clearance between copper items and edge cuts
86 #define LEGACY_COPPEREDGECLEARANCE -0.01 // A flag to indicate the legacy method (based
87  // on edge cut line thicknesses) should be used.
88 
89 #define MINIMUM_ERROR_SIZE_MM 0.001
90 #define MAXIMUM_ERROR_SIZE_MM 0.1
91 
92 #define DRC_EPSILON 5; // An epsilon to account for rounding errors, etc.
93  // 5nm is small enough not to materially violate
94  // any constraints.
95 
102 {
103  int m_Diameter; // <= 0 means use Netclass via diameter
104  int m_Drill; // <= 0 means use Netclass via drill
105 
107  {
108  m_Diameter = 0;
109  m_Drill = 0;
110  }
111 
112  VIA_DIMENSION( int aDiameter, int aDrill )
113  {
114  m_Diameter = aDiameter;
115  m_Drill = aDrill;
116  }
117 
118  bool operator==( const VIA_DIMENSION& aOther ) const
119  {
120  return ( m_Diameter == aOther.m_Diameter ) && ( m_Drill == aOther.m_Drill );
121  }
122 
123  bool operator<( const VIA_DIMENSION& aOther ) const
124  {
125  if( m_Diameter != aOther.m_Diameter )
126  return m_Diameter < aOther.m_Diameter;
127 
128  return m_Drill < aOther.m_Drill;
129  }
130 };
131 
132 
139 {
140  int m_Width; // <= 0 means use Netclass differential pair width
141  int m_Gap; // <= 0 means use Netclass differential pair gap
142  int m_ViaGap; // <= 0 means use Netclass differential pair via gap
143 
145  {
146  m_Width = 0;
147  m_Gap = 0;
148  m_ViaGap = 0;
149  }
150 
151  DIFF_PAIR_DIMENSION( int aWidth, int aGap, int aViaGap )
152  {
153  m_Width = aWidth;
154  m_Gap = aGap;
155  m_ViaGap = aViaGap;
156  }
157 
158  bool operator==( const DIFF_PAIR_DIMENSION& aOther ) const
159  {
160  return ( m_Width == aOther.m_Width )
161  && ( m_Gap == aOther.m_Gap )
162  && ( m_ViaGap == aOther.m_ViaGap );
163  }
164 
165  bool operator<( const DIFF_PAIR_DIMENSION& aOther ) const
166  {
167  if( m_Width != aOther.m_Width )
168  return m_Width < aOther.m_Width;
169 
170  if( m_Gap != aOther.m_Gap )
171  return m_Gap < aOther.m_Gap;
172 
173  return m_ViaGap < aOther.m_ViaGap;
174  }
175 };
176 
177 
178 enum
179 {
186 
188 };
189 
190 
192 {
193  wxString m_Text;
194  bool m_Visible;
195  int m_Layer;
196 
197  TEXT_ITEM_INFO( const wxString& aText, bool aVisible, int aLayer )
198  {
199  m_Text = aText;
200  m_Visible = aVisible;
201  m_Layer = aLayer;
202  }
203 };
204 
205 
206 // forward declaration from class_track.h
207 enum class VIATYPE : int;
208 
209 
215 {
216 public:
217  // Note: the first value in each dimensions list is the current netclass value
218  std::vector<int> m_TrackWidthList;
219  std::vector<VIA_DIMENSION> m_ViasDimensionsList;
220  std::vector<DIFF_PAIR_DIMENSION> m_DiffPairDimensionsList;
221 
222  // List of netclasses. There is always the default netclass.
223  //NETCLASSES m_NetClasses;
224  std::vector<DRC_SELECTOR*> m_DRCRuleSelectors;
225  std::vector<DRC_RULE*> m_DRCRules;
226 
227  // Temporary storage for rule matching.
228  std::vector<DRC_SELECTOR*> m_matched;
229 
233 
234  bool m_UseConnectedTrackWidth; // use width of existing track when creating a new,
235  // connected track
236  int m_MinClearance; // overall min clearance
237  int m_TrackMinWidth; // overall min track width
238  int m_ViasMinAnnulus; // overall minimum width of the via copper ring
239  int m_ViasMinSize; // overall vias (not micro vias) min diameter
240  int m_MinThroughDrill; // through hole (not micro vias) min drill diameter
241  int m_MicroViasMinSize; // micro vias min diameter
242  int m_MicroViasMinDrill; // micro vias min drill diameter
244  int m_HoleToHoleMin; // Min width of peninsula between two drilled holes
245 
246  std::map< int, int > m_DRCSeverities; // Map from DRCErrorCode to SEVERITY
247 
249  std::set<wxString> m_DrcExclusions;
250 
258 
259  // Maximum error allowed when approximating circles and arcs to segments
261 
262  // Global mask margins:
265  // 2 areas near than m_SolderMaskMinWidth
266  // are merged
269 
271  // Variables used in footprint editing (default value in item/footprint creation)
272  std::vector<TEXT_ITEM_INFO> m_DefaultFPTextItems;
273 
274  // Arrays of default values for the various layer classes.
275  int m_LineThickness[ LAYER_CLASS_COUNT ];
276  wxSize m_TextSize[ LAYER_CLASS_COUNT ];
277  int m_TextThickness[ LAYER_CLASS_COUNT ];
278  bool m_TextItalic[ LAYER_CLASS_COUNT ];
279  bool m_TextUpright[ LAYER_CLASS_COUNT ];
280 
283 
284  // Miscellaneous
287 
289  // when importing values or create a new pad
290 
299 
300 private:
301  // Indicies into the trackWidth, viaSizes and diffPairDimensions lists.
302  // The 0 index is always the current netclass value(s)
304  unsigned m_viaSizeIndex;
305  unsigned m_diffPairIndex;
306 
307  // Custom values for track/via sizes (specified via dialog instead of netclass or lists)
311 
312  // Custom values for differential pairs (specified via dialog instead of netclass/lists)
315 
317 
319 
321 
325 
331 
334 
337 
340 
341  SEVERITY severityFromString( const wxString& aSeverity );
342 
343  wxString severityToString( const SEVERITY& aSeverity );
344 
345 public:
346  BOARD_DESIGN_SETTINGS( JSON_SETTINGS* aParent, const std::string& aPath );
347 
348  virtual ~BOARD_DESIGN_SETTINGS();
349 
351 
352  bool LoadFromFile( const std::string& aDirectory = "" ) override;
353 
355 
356  int GetSeverity( int aDRCErrorCode );
357 
361  bool Ignore( int aDRCErrorCode );
362 
364  {
365  return *m_netClasses;
366  }
367 
368  void SetNetClasses( NETCLASSES* aNetClasses )
369  {
370  if( aNetClasses )
371  m_netClasses = aNetClasses;
372  else
373  m_netClasses = &m_internalNetClasses;
374  }
375 
377  {
378  return m_defaultZoneSettings;
379  }
380 
381  void SetDefaultZoneSettings( const ZONE_SETTINGS& aSettings )
382  {
383  m_defaultZoneSettings = aSettings;
384  }
385 
390  inline NETCLASS* GetDefault() const
391  {
392  return GetNetClasses().GetDefaultPtr();
393  }
394 
399  inline const wxString& GetCurrentNetClassName() const
400  {
401  return m_currentNetClassName;
402  }
403 
408  inline bool UseNetClassTrack() const
409  {
410  return ( m_trackWidthIndex == 0 && !m_useCustomTrackVia );
411  }
412 
417  inline bool UseNetClassVia() const
418  {
419  return ( m_viaSizeIndex == 0 && !m_useCustomTrackVia );
420  }
421 
426  inline bool UseNetClassDiffPair() const
427  {
428  return ( m_diffPairIndex == 0 && !m_useCustomDiffPair );
429  }
430 
439  bool SetCurrentNetClass( const wxString& aNetClassName );
440 
446 
452 
459 
466 
471  inline unsigned GetTrackWidthIndex() const { return m_trackWidthIndex; }
472 
479  void SetTrackWidthIndex( unsigned aIndex );
480 
487  inline int GetCurrentTrackWidth() const
488  {
489  return m_useCustomTrackVia ? m_customTrackWidth : m_TrackWidthList[m_trackWidthIndex];
490  }
491 
499  inline void SetCustomTrackWidth( int aWidth )
500  {
501  m_customTrackWidth = aWidth;
502  }
503 
508  inline int GetCustomTrackWidth() const
509  {
510  return m_customTrackWidth;
511  }
512 
517  inline unsigned GetViaSizeIndex() const
518  {
519  return m_viaSizeIndex;
520  }
521 
528  void SetViaSizeIndex( unsigned aIndex );
529 
536  inline int GetCurrentViaSize() const
537  {
538  if( m_useCustomTrackVia )
539  return m_customViaSize.m_Diameter;
540  else
541  return m_ViasDimensionsList[m_viaSizeIndex].m_Diameter;
542  }
543 
551  inline void SetCustomViaSize( int aSize )
552  {
553  m_customViaSize.m_Diameter = aSize;
554  }
555 
560  inline int GetCustomViaSize() const
561  {
562  return m_customViaSize.m_Diameter;
563  }
564 
571  int GetCurrentViaDrill() const;
572 
580  inline void SetCustomViaDrill( int aDrill )
581  {
582  m_customViaSize.m_Drill = aDrill;
583  }
584 
589  inline int GetCustomViaDrill() const
590  {
591  return m_customViaSize.m_Drill;
592  }
593 
601  inline void UseCustomTrackViaSize( bool aEnabled )
602  {
603  m_useCustomTrackVia = aEnabled;
604  }
605 
610  inline bool UseCustomTrackViaSize() const
611  {
612  return m_useCustomTrackVia;
613  }
614 
619  inline unsigned GetDiffPairIndex() const { return m_diffPairIndex; }
620 
625  void SetDiffPairIndex( unsigned aIndex );
626 
633  inline void SetCustomDiffPairWidth( int aWidth )
634  {
635  m_customDiffPair.m_Width = aWidth;
636  }
637 
643  {
644  return m_customDiffPair.m_Width;
645  }
646 
653  inline void SetCustomDiffPairGap( int aGap )
654  {
655  m_customDiffPair.m_Gap = aGap;
656  }
657 
662  inline int GetCustomDiffPairGap()
663  {
664  return m_customDiffPair.m_Gap;
665  }
666 
673  inline void SetCustomDiffPairViaGap( int aGap )
674  {
675  m_customDiffPair.m_ViaGap = aGap;
676  }
677 
683  {
684  return m_customDiffPair.m_ViaGap > 0 ? m_customDiffPair.m_ViaGap : m_customDiffPair.m_Gap;
685  }
686 
692  inline void UseCustomDiffPairDimensions( bool aEnabled )
693  {
694  m_useCustomDiffPair = aEnabled;
695  }
696 
701  inline bool UseCustomDiffPairDimensions() const
702  {
703  return m_useCustomDiffPair;
704  }
705 
712  inline int GetCurrentDiffPairWidth() const
713  {
714  if( m_useCustomDiffPair )
715  return m_customDiffPair.m_Width;
716  else
717  return m_DiffPairDimensionsList[m_diffPairIndex].m_Width;
718  }
719 
726  inline int GetCurrentDiffPairGap() const
727  {
728  if( m_useCustomDiffPair )
729  return m_customDiffPair.m_Gap;
730  else
731  return m_DiffPairDimensionsList[m_diffPairIndex].m_Gap;
732  }
733 
740  inline int GetCurrentDiffPairViaGap() const
741  {
742  if( m_useCustomDiffPair )
743  return m_customDiffPair.m_ViaGap;
744  else
745  return m_DiffPairDimensionsList[m_diffPairIndex].m_ViaGap;
746  }
747 
753  void SetMinHoleSeparation( int aDistance );
754 
759  void SetCopperEdgeClearance( int aDistance );
760 
766  inline LSET GetEnabledLayers() const
767  {
768  return m_enabledLayers;
769  }
770 
776  void SetEnabledLayers( LSET aMask );
777 
784  inline bool IsLayerEnabled( PCB_LAYER_ID aLayerId ) const
785  {
786  return m_enabledLayers[aLayerId];
787  }
788 
793  inline int GetCopperLayerCount() const
794  {
795  return m_copperLayerCount;
796  }
797 
803  void SetCopperLayerCount( int aNewLayerCount );
804 
805  inline int GetBoardThickness() const { return m_boardThickness; }
806  inline void SetBoardThickness( int aThickness ) { m_boardThickness = aThickness; }
807 
808  /*
809  * Function GetDRCEpsilon
810  * an epsilon which accounts for rounding errors, etc. While currently a global, going
811  * through this API allows us to easily change it to board-specific if so desired.
812  */
813  int GetDRCEpsilon() const { return DRC_EPSILON; }
814 
819  int GetLineThickness( PCB_LAYER_ID aLayer ) const;
820 
825  wxSize GetTextSize( PCB_LAYER_ID aLayer ) const;
826 
831  int GetTextThickness( PCB_LAYER_ID aLayer ) const;
832 
833  bool GetTextItalic( PCB_LAYER_ID aLayer ) const;
834  bool GetTextUpright( PCB_LAYER_ID aLayer ) const;
835 
836  int GetLayerClass( PCB_LAYER_ID aLayer ) const;
837 };
838 
839 #endif // BOARD_DESIGN_SETTINGS_H_
int GetCurrentMicroViaSize()
Function GetCurrentMicroViaSize.
int m_SolderMaskMargin
Solder mask margin.
bool UseNetClassTrack() const
Function UseNetClassTrack returns true if netclass values should be used to obtain appropriate track ...
void SetNetClasses(NETCLASSES *aNetClasses)
void SetCopperLayerCount(int aNewLayerCount)
Function SetCopperLayerCount do what its name says...
Struct VIA_DIMENSION is a small helper container to handle a stock of specific vias each with unique ...
void SetEnabledLayers(LSET aMask)
Function SetEnabledLayers changes the bit-mask of enabled layers.
void SetCopperEdgeClearance(int aDistance)
Function SetCopperEdgeClearance.
bool UseCustomDiffPairDimensions() const
Function UseCustomDiffPairDimensions.
void SetTrackWidthIndex(unsigned aIndex)
Function SetTrackWidthIndex sets the current track width list index to aIndex.
int GetCustomViaSize() const
Function GetCustomViaSize.
wxString m_currentNetClassName
Current net class name used to display netclass info.
std::vector< TEXT_ITEM_INFO > m_DefaultFPTextItems
wxPoint m_GridOrigin
origin for grid offsets
int GetCurrentViaDrill() const
Function GetCurrentViaDrill.
int m_SolderPasteMargin
Solder paste margin absolute value.
int GetCurrentTrackWidth() const
Function GetCurrentTrackWidth.
this class manage the layers needed to make a physical board they are solder mask,...
void SetCustomDiffPairViaGap(int aGap)
Function SetCustomDiffPairViaGap Sets custom via gap for differential pairs (i.e.
BOARD_DESIGN_SETTINGS(JSON_SETTINGS *aParent, const std::string &aPath)
std::vector< int > m_TrackWidthList
void SetDefaultZoneSettings(const ZONE_SETTINGS &aSettings)
int GetSmallestClearanceValue()
Function GetSmallestClearanceValue.
int GetBiggestClearanceValue()
Function GetBiggestClearanceValue.
bool IsLayerEnabled(PCB_LAYER_ID aLayerId) const
Function IsLayerEnabled tests whether a given layer is enabled.
BOARD_STACKUP m_stackup
the description of layers stackup, for board fabrication only physical layers are in layers stackup.
SEVERITY
Definition: ui_common.h:45
int GetCurrentDiffPairGap() const
Function GetCurrentDiffPairGap.
int GetCurrentMicroViaDrill()
Function GetCurrentMicroViaDrill.
bool UseNetClassDiffPair() const
Function UseNetClassDiffPair returns true if netclass values should be used to obtain appropriate dif...
std::vector< DIFF_PAIR_DIMENSION > m_DiffPairDimensionsList
std::map< int, int > m_DRCSeverities
void SetCustomViaDrill(int aDrill)
Function SetCustomViaDrill Sets custom size for via drill (i.e.
NETCLASSES m_internalNetClasses
Net classes that are loaded from the board file before these were stored in the project.
std::vector< DRC_SELECTOR * > m_DRCRuleSelectors
bool Ignore(int aDRCErrorCode)
returns true if the DRC error code's severity is SEVERITY_IGNORE
void UseCustomDiffPairDimensions(bool aEnabled)
Function UseCustomDiffPairDimensions Enables/disables custom differential pair dimensions.
bool operator<(const VIA_DIMENSION &aOther) const
ZONE_SETTINGS m_defaultZoneSettings
The defualt settings that will be used for new zones.
bool operator<(const DIFF_PAIR_DIMENSION &aOther) const
DIFF_PAIR_DIMENSION m_customDiffPair
int GetTextThickness(PCB_LAYER_ID aLayer) const
Function GetTextThickness Returns the default text thickness from the layer class for the given layer...
TEXT_ITEM_INFO(const wxString &aText, bool aVisible, int aLayer)
void SetBoardThickness(int aThickness)
VIATYPE m_CurrentViaType
(VIA_BLIND_BURIED, VIA_THROUGH, VIA_MICROVIA)
Struct DIFF_PAIR_DIMENSION is a small helper container to handle a stock of specific differential pai...
void SetCustomViaSize(int aSize)
Function SetCustomViaSize Sets custom size for via diameter (i.e.
int GetCustomDiffPairWidth()
Function GetCustomDiffPairWidth.
int GetLayerClass(PCB_LAYER_ID aLayer) const
bool GetTextUpright(PCB_LAYER_ID aLayer) const
bool GetTextItalic(PCB_LAYER_ID aLayer) const
int GetLineThickness(PCB_LAYER_ID aLayer) const
Function GetLineThickness Returns the default graphic segment thickness from the layer class for the ...
bool UseCustomTrackViaSize() const
Function UseCustomTrackViaSize.
int GetCustomViaDrill() const
Function GetCustomViaDrill.
void SetViaSizeIndex(unsigned aIndex)
Function SetViaSizeIndex sets the current via size list index to aIndex.
NESTED_SETTINGS is a JSON_SETTINGS that lives inside a JSON_SETTINGS.
wxString severityToString(const SEVERITY &aSeverity)
BOARD_STACKUP & GetStackupDescriptor()
PCB_LAYER_ID
A quick note on layer IDs:
LSET is a set of PCB_LAYER_IDs.
NETCLASSES is a container for NETCLASS instances.
Definition: netclass.h:221
std::vector< DRC_SELECTOR * > m_matched
const wxString & GetCurrentNetClassName() const
Function GetCurrentNetClassName.
unsigned GetViaSizeIndex() const
Function GetViaSizeIndex.
void SetMinHoleSeparation(int aDistance)
Function SetMinHoleSeparation.
bool UseNetClassVia() const
Function UseNetClassVia returns true if netclass values should be used to obtain appropriate via size...
void SetCustomDiffPairWidth(int aWidth)
Function SetCustomDiffPairWidth Sets custom track width for differential pairs (i....
int GetCustomTrackWidth() const
Function GetCustomTrackWidth.
NETCLASS handles a collection of nets and the parameters used to route or test these nets.
Definition: netclass.h:55
VIATYPE
Definition: class_track.h:68
int GetCurrentDiffPairWidth() const
Function GetCurrentDiffPairWidth.
unsigned GetTrackWidthIndex() const
Function GetTrackWidthIndex.
bool LoadFromFile(const std::string &aDirectory="") override
Loads the backing file from disk and then calls Load()
Functions to provide common constants and other functions to assist in making a consistent UI.
BOARD_DESIGN_SETTINGS & operator=(const BOARD_DESIGN_SETTINGS &aOther)
NETCLASSES & GetNetClasses() const
bool m_BlindBuriedViaAllowed
true to allow blind/buried vias
void SetDiffPairIndex(unsigned aIndex)
Function SetDiffPairIndex.
void SetCustomDiffPairGap(int aGap)
Function SetCustomDiffPairGap Sets custom gap for differential pairs (i.e.
NETCLASS * GetDefaultPtr() const
Definition: netclass.h:270
void SetCustomTrackWidth(int aWidth)
Function SetCustomTrackWidth Sets custom width for track (i.e.
Pad object description.
ZONE_SETTINGS handles zones parameters.
Definition: zone_settings.h:67
bool operator==(const VIA_DIMENSION &aOther) const
int GetCurrentViaSize() const
Function GetCurrentViaSize.
bool SetCurrentNetClass(const wxString &aNetClassName)
Function SetCurrentNetClass Must be called after a netclass selection (or after a netclass parameter ...
SEVERITY severityFromString(const wxString &aSeverity)
LSET GetEnabledLayers() const
Function GetEnabledLayers returns a bit-mask of all the layers that are enabled.
int GetCustomDiffPairViaGap()
Function GetCustomDiffPairViaGap.
bool m_ZoneUseNoOutlineInFill
Option to handle filled polygons in zones: the "legacy" option is using thick outlines around filled ...
#define DRC_EPSILON
D_PAD m_Pad_Master
A dummy pad to store all default parameters.
NETCLASS * GetDefault() const
Function GetDefault.
int GetCurrentDiffPairViaGap() const
Function GetCurrentDiffPairViaGap.
std::vector< VIA_DIMENSION > m_ViasDimensionsList
DIFF_PAIR_DIMENSION(int aWidth, int aGap, int aViaGap)
bool operator==(const DIFF_PAIR_DIMENSION &aOther) const
VIA_DIMENSION(int aDiameter, int aDrill)
unsigned GetDiffPairIndex() const
Function GetDiffPairIndex.
NETCLASSES * m_netClasses
This will point to m_internalNetClasses until it is repointed to the project after load.
ZONE_SETTINGS & GetDefaultZoneSettings()
int m_copperLayerCount
Number of copper layers for this design.
bool m_MicroViasAllowed
true to allow micro vias
bool m_HasStackup
Set to true if the board has a stackup management.
double m_SolderPasteMarginRatio
Solder pask margin ratio value of pad size The final margin is the sum of these 2 values.
int GetSeverity(int aDRCErrorCode)
std::set< wxString > m_DrcExclusions
Excluded DRC items.
int GetCopperLayerCount() const
Function GetCopperLayerCount.
LSET m_enabledLayers
Bit-mask for layer enabling.
std::vector< DRC_RULE * > m_DRCRules
wxPoint m_AuxOrigin
origin for plot exports
wxSize GetTextSize(PCB_LAYER_ID aLayer) const
Function GetTextSize Returns the default text size from the layer class for the given layer.
int m_boardThickness
Board thickness for 3D viewer.
int GetCustomDiffPairGap()
Function GetCustomDiffPairGap.
void UseCustomTrackViaSize(bool aEnabled)
Function UseCustomTrackViaSize Enables/disables custom track/via size settings.
int m_SolderMaskMinWidth
Solder mask min width.
BOARD_DESIGN_SETTINGS contains design settings for a BOARD object.