KiCad PCB EDA Suite
sch_connection.cpp File Reference
#include <regex>
#include <wx/tokenzr.h>
#include <advanced_config.h>
#include <connection_graph.h>
#include <sch_component.h>
#include <sch_pin.h>
#include <sch_screen.h>
#include <sch_connection.h>

Go to the source code of this file.


static std::regex bus_label_re ("^([^[:space:]]+)(\\[[\\d]+\\.+[\\d]+\\])(~?)$")
 Buses can be defined in multiple ways. More...
static std::regex bus_group_label_re ("^([^[:space:]]+)?\\{((?:[^[:space:]]+(?:\\[[\\d]+\\.+[\\d]+\\])? ?)+)\\}$")

Function Documentation

◆ bus_group_label_re()

static std::regex bus_group_label_re ( "^([^[:space:]]+)?\\{((?:[^[:space:]]+(?:\\[[\\d]+\\.+[\\d]+\\])? ?)+)\\}$"  )

◆ bus_label_re()

static std::regex bus_label_re ( "^([^[:space:]]+)(\\[[\\d]+\\.+[\\d]+\\])(~?)$"  )

Buses can be defined in multiple ways.

A bus vector consists of a prefix and a numeric range of suffixes:


For example, the bus A[3..0] will contain nets A3, A2, A1, and A0. The BUS_NAME is required. M and N must be integers but do not need to be in any particular order – A[0..3] produces the same result.

Like net names, bus names cannot contain whitespace.

A bus group is just a grouping of signals, separated by spaces, some of which may be bus vectors. Bus groups can have names, but do not need to.

MEMORY{A[15..0] D[7..0] RW CE OE}

In named bus groups, the net names are expanded as <BUS_NAME>.<NET_NAME> In the above example, the nets would be named like MEMORY.A15, MEMORY.D0, etc.


In the above example, the bus is unnamed and so the underlying net names are just USB_DP and USB_DN.

Referenced by SCH_CONNECTION::IsBusVectorLabel(), and SCH_CONNECTION::ParseBusVector().