KiCad PCB EDA Suite
class_board_design_settings.cpp
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23 
29 #include <fctsys.h>
30 #include <common.h>
32 
33 #include <pcbnew.h>
35 
36 #include <class_track.h>
37 #include <convert_to_biu.h>
38 
39 
41  m_Pad_Master( NULL )
42 {
43  LSET all_set = LSET().set();
44 
45  m_enabledLayers = all_set; // All layers enabled at first.
46  // SetCopperLayerCount() will adjust this.
47  SetVisibleLayers( all_set );
48 
49  // set all but hidden text as visible.
51 
52  SetCopperLayerCount( 2 ); // Default design is a double sided board
53 
54  // via type (VIA_BLIND_BURIED, VIA_THROUGH VIA_MICROVIA).
56 
57  // if true, when creating a new track starting on an existing track, use this track width
59 
60  m_BlindBuriedViaAllowed = false; // true to allow blind/buried vias
61  m_MicroViasAllowed = false; // true to allow micro vias
62 
63  m_DrawSegmentWidth = Millimeter2iu( DEFAULT_GRAPHIC_THICKNESS ); // current graphic line width (not EDGE layer)
64 
65  m_EdgeSegmentWidth = Millimeter2iu( DEFAULT_PCB_EDGE_THICKNESS ); // current graphic line width (EDGE layer only)
66  m_PcbTextWidth = Millimeter2iu( DEFAULT_TEXT_PCB_THICKNESS ); // current Pcb (not module) Text width
67 
68  m_PcbTextSize = wxSize( Millimeter2iu( DEFAULT_TEXT_PCB_SIZE ),
69  Millimeter2iu( DEFAULT_TEXT_PCB_SIZE ) ); // current Pcb (not module) Text size
70 
71  m_useCustomTrackVia = false;
74  m_customViaSize.m_Drill = Millimeter2iu( DEFAULT_VIASMINDRILL );
75 
76  m_TrackMinWidth = Millimeter2iu( DEFAULT_TRACKMINWIDTH ); // track min width
77  m_ViasMinSize = Millimeter2iu( DEFAULT_VIASMINSIZE ); // via (not uvia) min diam
78  m_ViasMinDrill = Millimeter2iu( DEFAULT_VIASMINDRILL ); // via (not uvia) min drill diam
79  m_MicroViasMinSize = Millimeter2iu( DEFAULT_MICROVIASMINSIZE );// uvia (not via) min diam
80  m_MicroViasMinDrill = Millimeter2iu( DEFAULT_MICROVIASMINDRILL );// uvia (not via) min drill diam
81 
82  // Global mask margins:
83  m_SolderMaskMargin = Millimeter2iu( DEFAULT_SOLDERMASK_CLEARANCE ); // Solder mask margin
84  m_SolderMaskMinWidth = Millimeter2iu( DEFAULT_SOLDERMASK_MIN_WIDTH ); // Solder mask min width
85  m_SolderPasteMargin = 0; // Solder paste margin absolute value
86  m_SolderPasteMarginRatio = 0.0; // Solder pask margin ratio value of pad size
87  // The final margin is the sum of these 2 values
88  // Usually < 0 because the mask is smaller than pad
89 
90  // Layer thickness for 3D viewer
92 
93  m_viaSizeIndex = 0;
95 
96  // Default values for the footprint editor and fp creation
97  // (also covers footprints created on the fly by micor-waves tools)
98  m_ModuleTextSize = wxSize( Millimeter2iu( DEFAULT_TEXT_MODULE_SIZE ),
99  Millimeter2iu( DEFAULT_TEXT_MODULE_SIZE ) );
102 
103  // These values will be overriden by config values after reading the config
104  // Default ref text on fp creation. if empty, use footprint name as default
105  m_RefDefaultText = wxT( "REF**" );
106  m_RefDefaultVisibility = true; // Default ref text visibility on fp creation
107  m_RefDefaultlayer = int( F_SilkS ); // Default ref text layer on fp creation
108  // Default value text on fp creation. if empty, use footprint name as default
109  m_ValueDefaultText = wxEmptyString;
111  m_ValueDefaultlayer = int( F_Fab );
112 }
113 
114 // Add parameters to save in project config.
115 // values are saved in mm
117 {
118  m_Pad_Master.AppendConfigs( aResult );
119 
120  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "PcbTextSizeV" ),
121  &m_PcbTextSize.y,
123  NULL, MM_PER_IU ) );
124 
125  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "PcbTextSizeH" ),
126  &m_PcbTextSize.x,
128  NULL, MM_PER_IU ) );
129 
130  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "PcbTextThickness" ),
132  Millimeter2iu(DEFAULT_TEXT_PCB_THICKNESS ),
133  Millimeter2iu( 0.01 ), Millimeter2iu( 5.0 ),
134  NULL, MM_PER_IU ) );
135 
136  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "ModuleTextSizeV" ),
137  &m_ModuleTextSize.y,
139  NULL, MM_PER_IU ) );
140 
141  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "ModuleTextSizeH" ),
142  &m_ModuleTextSize.x,
144  NULL, MM_PER_IU ) );
145 
146  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "ModuleTextSizeThickness" ),
148  Millimeter2iu( DEFAULT_GR_MODULE_THICKNESS ), 1, TEXTS_MAX_WIDTH,
149  NULL, MM_PER_IU ) );
150 
151  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "SolderMaskClearance" ),
153  Millimeter2iu( DEFAULT_SOLDERMASK_CLEARANCE ), 0, Millimeter2iu( 1.0 ),
154  NULL, MM_PER_IU ) );
155 
156  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "SolderMaskMinWidth" ),
158  Millimeter2iu( DEFAULT_SOLDERMASK_MIN_WIDTH ), 0, Millimeter2iu( 0.5 ),
159  NULL, MM_PER_IU ) );
160 
161  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "DrawSegmentWidth" ),
163  Millimeter2iu( DEFAULT_GRAPHIC_THICKNESS ),
164  Millimeter2iu( 0.01 ), Millimeter2iu( 5.0 ),
165  NULL, MM_PER_IU ) );
166 
167  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "BoardOutlineThickness" ),
169  Millimeter2iu( DEFAULT_PCB_EDGE_THICKNESS ),
170  Millimeter2iu( 0.01 ), Millimeter2iu( 5.0 ),
171  NULL, MM_PER_IU ) );
172 
173  aResult->push_back( new PARAM_CFG_INT_WITH_SCALE( wxT( "ModuleOutlineThickness" ),
175  Millimeter2iu( DEFAULT_GR_MODULE_THICKNESS ),
176  Millimeter2iu( 0.01 ), Millimeter2iu( 5.0 ),
177  NULL, MM_PER_IU ) );
178 }
179 
180 
181 bool BOARD_DESIGN_SETTINGS::SetCurrentNetClass( const wxString& aNetClassName )
182 {
183  NETCLASSPTR netClass = m_NetClasses.Find( aNetClassName );
184  bool lists_sizes_modified = false;
185 
186  // if not found (should not happen) use the default
187  if( netClass == NULL )
188  netClass = m_NetClasses.GetDefault();
189 
190  m_currentNetClassName = netClass->GetName();
191 
192  // Initialize others values:
193  if( m_ViasDimensionsList.size() == 0 )
194  {
195  VIA_DIMENSION viadim;
196  lists_sizes_modified = true;
197  m_ViasDimensionsList.push_back( viadim );
198  }
199 
200  if( m_TrackWidthList.size() == 0 )
201  {
202  lists_sizes_modified = true;
203  m_TrackWidthList.push_back( 0 );
204  }
205 
206  /* note the m_ViasDimensionsList[0] and m_TrackWidthList[0] values
207  * are always the Netclass values
208  */
209  if( m_ViasDimensionsList[0].m_Diameter != netClass->GetViaDiameter() )
210  {
211  lists_sizes_modified = true;
212  m_ViasDimensionsList[0].m_Diameter = netClass->GetViaDiameter();
213  }
214 
215  if( m_ViasDimensionsList[0].m_Drill != netClass->GetViaDrill() )
216  {
217  lists_sizes_modified = true;
218  m_ViasDimensionsList[0].m_Drill = netClass->GetViaDrill();
219  }
220 
221  if( m_TrackWidthList[0] != netClass->GetTrackWidth() )
222  {
223  lists_sizes_modified = true;
224  m_TrackWidthList[0] = netClass->GetTrackWidth();
225  }
226 
227  if( GetViaSizeIndex() >= m_ViasDimensionsList.size() )
229 
230  if( GetTrackWidthIndex() >= m_TrackWidthList.size() )
232 
233  return lists_sizes_modified;
234 }
235 
236 
238 {
239  int clearance = m_NetClasses.GetDefault()->GetClearance();
240 
241  //Read list of Net Classes
242  for( NETCLASSES::const_iterator nc = m_NetClasses.begin(); nc != m_NetClasses.end(); ++nc )
243  {
244  NETCLASSPTR netclass = nc->second;
245  clearance = std::max( clearance, netclass->GetClearance() );
246  }
247 
248  return clearance;
249 }
250 
251 
253 {
254  int clearance = m_NetClasses.GetDefault()->GetClearance();
255 
256  //Read list of Net Classes
257  for( NETCLASSES::const_iterator nc = m_NetClasses.begin(); nc != m_NetClasses.end(); ++nc )
258  {
259  NETCLASSPTR netclass = nc->second;
260  clearance = std::min( clearance, netclass->GetClearance() );
261  }
262 
263  return clearance;
264 }
265 
266 
268 {
269  NETCLASSPTR netclass = m_NetClasses.Find( m_currentNetClassName );
270 
271  return netclass->GetuViaDiameter();
272 }
273 
274 
276 {
277  NETCLASSPTR netclass = m_NetClasses.Find( m_currentNetClassName );
278 
279  return netclass->GetuViaDrill();
280 }
281 
282 
284 {
285  if( aIndex >= m_ViasDimensionsList.size() )
287  else
288  m_viaSizeIndex = aIndex;
289 
290  m_useCustomTrackVia = false;
291 }
292 
293 
295 {
296  int drill;
297 
298  if( m_useCustomTrackVia )
299  drill = m_customViaSize.m_Drill;
300  else
301  drill = m_ViasDimensionsList[m_viaSizeIndex].m_Drill;
302 
303  return drill > 0 ? drill : -1;
304 }
305 
306 
308 {
309  if( aIndex >= m_TrackWidthList.size() )
311  else
312  m_trackWidthIndex = aIndex;
313 
314  m_useCustomTrackVia = false;
315 }
316 
317 
319 {
320  SetVisibleLayers( LSET().set() );
321  m_visibleElements = -1;
322 }
323 
324 
326 {
327  if( aNewState && IsLayerEnabled( aLayer ) )
328  m_visibleLayers.set( aLayer, true );
329  else
330  m_visibleLayers.set( aLayer, false );
331 }
332 
333 
334 void BOARD_DESIGN_SETTINGS::SetElementVisibility( GAL_LAYER_ID aElementCategory, bool aNewState )
335 {
336  if( aNewState )
337  m_visibleElements |= 1 << GAL_LAYER_INDEX( aElementCategory );
338  else
339  m_visibleElements &= ~( 1 << GAL_LAYER_INDEX( aElementCategory ) );
340 }
341 
342 
344 {
345  // if( aNewLayerCount < 2 ) aNewLayerCount = 2;
346 
347  m_copperLayerCount = aNewLayerCount;
348 
349  // ensure consistency with the m_EnabledLayers member
350 #if 0
351  // was:
354 
355  if( m_copperLayerCount > 1 )
357 
358  for( LAYER_NUM ii = LAYER_N_2; ii < aNewLayerCount - 1; ++ii )
359  m_enabledLayers |= GetLayerSet( ii );
360 #else
361  // Update only enabled copper layers mask
362  m_enabledLayers &= ~LSET::AllCuMask();
363  m_enabledLayers |= LSET::AllCuMask( aNewLayerCount );
364 #endif
365 }
366 
367 
369 {
370  // Back and front layers are always enabled.
371  aMask.set( B_Cu ).set( F_Cu );
372 
373  m_enabledLayers = aMask;
374 
375  // A disabled layer cannot be visible
376  m_visibleLayers &= aMask;
377 
378  // update m_CopperLayerCount to ensure its consistency with m_EnabledLayers
379  m_copperLayerCount = ( aMask & LSET::AllCuMask() ).count();
380 }
381 
382 
383 #ifndef NDEBUG
386  {
387  // Int (the type used for saving visibility settings) is only 32 bits guaranteed,
388  // be sure that we do not cross the limit
389  assert( GAL_LAYER_INDEX( GAL_LAYER_ID_BITMASK_END ) <= 32 );
390  };
391 };
393 #endif
int GetCurrentMicroViaSize()
Function GetCurrentMicroViaSize.
static LSET AllCuMask(int aCuLayerCount=MAX_CU_LAYERS)
Function AllCuMask returns a mask holding the requested number of Cu PCB_LAYER_IDs.
Definition: lset.cpp:639
unsigned m_trackWidthIndex
0 is the index selection of the default value Netclass
wxString m_RefDefaultText
Default ref text on fp creation.
int m_SolderMaskMargin
Solder mask margin.
VIA_DIMENSION m_customViaSize
Custom via size (used after UseCustomTrackViaSize( true ) was called).
void SetCopperLayerCount(int aNewLayerCount)
Function SetCopperLayerCount do what its name says...
Struct VIA_DIMENSION is a small helper container to handle a stock of specific vias each with unique ...
void SetEnabledLayers(LSET aMask)
Function SetEnabledLayers changes the bit-mask of enabled layers.
A list of parameters type.
bool m_ValueDefaultVisibility
Default value text visibility on fp creation.
void SetTrackWidthIndex(unsigned aIndex)
Function SetTrackWidthIndex sets the current track width list index to aIndex.
VIATYPE_T m_CurrentViaType
via type (VIA_BLIND_BURIED, VIA_THROUGH VIA_MICROVIA)
int GetCurrentViaDrill() const
Function GetCurrentViaDrill.
wxString m_currentNetClassName
Current net class name used to display netclass info.
NETCLASSPTR Find(const wxString &aName) const
Function Find searches this container for a NETCLASS given by aName.
int m_SolderPasteMargin
Solder paste margin absolute value.
#define LAYER_FRONT
bit mask for component layer
#define TEXTS_MAX_WIDTH
Maximum text width in Pcbnew units value (0.5 inches)
Definition: pcbnew.h:64
int m_ModuleTextWidth
Default footprint texts thickness.
std::vector< int > m_TrackWidthList
Track width list.
int m_ModuleSegmentWidth
Default width for all graphic lines.
int GetSmallestClearanceValue()
Function GetSmallestClearanceValue.
int GetBiggestClearanceValue()
Function GetBiggestClearanceValue.
int GetCurrentMicroViaDrill()
Function GetCurrentMicroViaDrill.
int m_PcbTextWidth
current Pcb (not module) Text width
void SetLayerVisibility(PCB_LAYER_ID aLayerId, bool aNewState)
Function SetLayerVisibility changes the visibility of a given layer.
bool IsLayerEnabled(PCB_LAYER_ID aLayerId) const
Function IsLayerEnabled tests whether a given layer is enabled.
bool m_useCustomTrackVia
Use custom values for track/via sizes (not specified in net class nor in the size lists)...
GAL_LAYER_ID
GAL layers are "virtual" layers, i.e.
iterator end()
int m_ValueDefaultlayer
Default value text layer on fp creation.
#define DEFAULT_SOLDERMASK_CLEARANCE
#define DEFAULT_VIASMINDRILL
void SetVisibleAlls()
Function SetVisibleAlls Set the bit-mask of all visible elements categories, including enabled layers...
This is the end of the layers used for visibility bitmasks in Pcbnew There can be at most 32 layers a...
wxSize m_ModuleTextSize
Default footprint texts size.
Configuration parameter - Integer Class with unit conversion.
bool m_UseConnectedTrackWidth
if true, when creating a new track starting on an existing track, use this track width ...
NETCLASS_MAP::const_iterator const_iterator
Functions relatives to tracks, vias and segments used to fill zones.
#define DEFAULT_PCB_EDGE_THICKNESS
#define DEFAULT_TEXT_MODULE_SIZE
unsigned GetViaSizeIndex() const
Function GetViaSizeIndex.
void SetVisibleLayers(LSET aMask)
Function SetVisibleLayers changes the bit-mask of visible layers.
void SetViaSizeIndex(unsigned aIndex)
Function SetViaSizeIndex sets the current via size list index to aIndex.
#define DEFAULT_GRAPHIC_THICKNESS
PCB_LAYER_ID
A quick note on layer IDs:
Class LSET is a set of PCB_LAYER_IDs.
iterator begin()
#define DEFAULT_GR_MODULE_THICKNESS
#define GAL_LAYER_INDEX(x)
Use this macro to convert a GAL layer to a 0-indexed offset from LAYER_VIAS.
wxSize m_PcbTextSize
current Pcb (not module) Text size
int m_TrackMinWidth
track min value for width ((min copper size value
static list_size_check check
int m_ViasMinSize
vias (not micro vias) min diameter
#define DEFAULT_TEXT_PCB_THICKNESS
#define DEFAULT_CUSTOMTRACKWIDTH
int m_DrawSegmentWidth
current graphic line width (not EDGE layer)
int m_ViasMinDrill
vias (not micro vias) min drill diameter
bool m_BlindBuriedViaAllowed
true to allow blind/buried vias
#define ALL_CU_LAYERS
#define TEXTS_MAX_SIZE
Maximum text size in Pcbnew units value (1 inch) )
Definition: pcbnew.h:63
wxString m_ValueDefaultText
Default value text on fp creation.
#define DEFAULT_BOARD_THICKNESS_MM
int m_MicroViasMinSize
micro vias (not vias) min diameter
#define TEXTS_MIN_SIZE
Minimum text size in Pcbnew units value (5 mils)
Definition: pcbnew.h:62
int LAYER_NUM
Type LAYER_NUM can be replaced with int and removed.
LSET m_visibleLayers
Bit-mask for layer visibility.
#define DEFAULT_MICROVIASMINDRILL
int m_visibleElements
Bit-mask for element category visibility.
bool SetCurrentNetClass(const wxString &aNetClassName)
Function SetCurrentNetClass Must be called after a netclass selection (or after a netclass parameter ...
Board layer functions and definitions.
#define max(a, b)
Definition: auxiliary.h:86
unsigned m_viaSizeIndex
Index for m_ViasDimensionsList to select the current via size.
#define LAYER_BACK
bit mask for copper layer
NETCLASSPTR GetDefault() const
Function GetDefault.
D_PAD m_Pad_Master
A dummy pad to store all default parameters.
#define DEFAULT_MICROVIASMINSIZE
int m_RefDefaultlayer
Default ref text layer on fp creation.
The common library.
#define DEFAULT_SOLDERMASK_MIN_WIDTH
void SetElementVisibility(GAL_LAYER_ID aElementCategory, bool aNewState)
Function SetElementVisibility changes the visibility of an element category.
std::vector< VIA_DIMENSION > m_ViasDimensionsList
Vias size and drill list.
unsigned GetTrackWidthIndex() const
Function GetTrackWidthIndex.
#define LAYER_N_2
void AppendConfigs(PARAM_CFG_ARRAY *aResult)
Function AppendConfigs appends to aResult the configuration setting accessors which will later allow ...
int m_copperLayerCount
Number of copper layers for this design.
bool m_MicroViasAllowed
true to allow micro vias
int m_MicroViasMinDrill
micro vias (not vias) min drill diameter
int m_EdgeSegmentWidth
current graphic line width (EDGE layer only)
double m_SolderPasteMarginRatio
Solder pask margin ratio value of pad size The final margin is the sum of these 2 values...
#define DEFAULT_TRACKMINWIDTH
LSET m_enabledLayers
Bit-mask for layer enabling.
bool m_RefDefaultVisibility
Default ref text visibility on fp creation.
int m_boardThickness
Board thickness for 3D viewer.
NETCLASSES m_NetClasses
List of current netclasses. There is always the default netclass.
int m_SolderMaskMinWidth
Solder mask min width.
int m_customTrackWidth
Custom track width (used after UseCustomTrackViaSize( true ) was called).
#define min(a, b)
Definition: auxiliary.h:85
#define DEFAULT_VIASMINSIZE
#define DEFAULT_TEXT_PCB_SIZE
void AppendConfigs(PARAM_CFG_ARRAY *aResult)
Function AppendConfigs appends to aResult the configuration setting accessors which will later allow ...
Definition: class_pad.cpp:468