KiCad PCB EDA Suite
board_design_settings.h
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24 
25 #ifndef BOARD_DESIGN_SETTINGS_H_
26 #define BOARD_DESIGN_SETTINGS_H_
27 
28 #include <class_pad.h>
29 #include <class_track.h>
30 #include <netclass.h>
31 #include <config_params.h>
32 
33 #define DEFAULT_SILK_LINE_WIDTH 0.12
34 #define DEFAULT_COPPER_LINE_WIDTH 0.20
35 #define DEFAULT_EDGE_WIDTH 0.05
36 #define DEFAULT_COURTYARD_WIDTH 0.05
37 #define DEFAULT_LINE_WIDTH 0.10
38 
39 #define DEFAULT_SILK_TEXT_SIZE 1.0
40 #define DEFAULT_COPPER_TEXT_SIZE 1.5
41 #define DEFAULT_TEXT_SIZE 1.0
42 
43 #define DEFAULT_SILK_TEXT_WIDTH 0.15
44 #define DEFAULT_COPPER_TEXT_WIDTH 0.30
45 #define DEFAULT_TEXT_WIDTH 0.15
46 
47 // Board thickness, mainly for 3D view:
48 #define DEFAULT_BOARD_THICKNESS_MM 1.6
49 
50 #define DEFAULT_PCB_EDGE_THICKNESS 0.15
51 
52 #define DEFAULT_SOLDERMASK_CLEARANCE 0.051 // soldermask to pad clearance
53 #define DEFAULT_SOLDERMASK_MIN_WIDTH 0.25 // soldermask minimum dam size
54 #define DEFAULT_SOLDERPASTE_CLEARANCE 0.0
55 #define DEFAULT_SOLDERPASTE_RATIO 0.0
56 
57 #define DEFAULT_CUSTOMTRACKWIDTH 0.2
58 #define DEFAULT_CUSTOMDPAIRWIDTH 0.125
59 #define DEFAULT_CUSTOMDPAIRGAP 0.18
60 #define DEFAULT_CUSTOMDPAIRVIAGAP 0.18
61 
62 #define DEFAULT_TRACKMINWIDTH 0.2 // track width min value
63 #define DEFAULT_VIASMINSIZE 0.4 // vias (not micro vias) min diameter
64 #define DEFAULT_VIASMINDRILL 0.3 // vias (not micro vias) min drill diameter
65 #define DEFAULT_MICROVIASMINSIZE 0.2 // micro vias (not vias) min diameter
66 #define DEFAULT_MICROVIASMINDRILL 0.1 // micro vias (not vias) min drill diameter
67 #define DEFAULT_HOLETOHOLEMIN 0.25 // separation between drilled hole edges
68 
75 {
76  int m_Diameter; // <= 0 means use Netclass via diameter
77  int m_Drill; // <= 0 means use Netclass via drill
78 
80  {
81  m_Diameter = 0;
82  m_Drill = 0;
83  }
84 
85  VIA_DIMENSION( int aDiameter, int aDrill )
86  {
87  m_Diameter = aDiameter;
88  m_Drill = aDrill;
89  }
90 
91  bool operator==( const VIA_DIMENSION& aOther ) const
92  {
93  return ( m_Diameter == aOther.m_Diameter ) && ( m_Drill == aOther.m_Drill );
94  }
95 
96  bool operator<( const VIA_DIMENSION& aOther ) const
97  {
98  if( m_Diameter != aOther.m_Diameter )
99  return m_Diameter < aOther.m_Diameter;
100 
101  return m_Drill < aOther.m_Drill;
102  }
103 };
104 
105 
112 {
113  int m_Width; // <= 0 means use Netclass differential pair width
114  int m_Gap; // <= 0 means use Netclass differential pair gap
115  int m_ViaGap; // <= 0 means use Netclass differential pair via gap
116 
118  {
119  m_Width = 0;
120  m_Gap = 0;
121  m_ViaGap = 0;
122  }
123 
124  DIFF_PAIR_DIMENSION( int aWidth, int aGap, int aViaGap )
125  {
126  m_Width = aWidth;
127  m_Gap = aGap;
128  m_ViaGap = aViaGap;
129  }
130 
131  bool operator==( const DIFF_PAIR_DIMENSION& aOther ) const
132  {
133  return ( m_Width == aOther.m_Width )
134  && ( m_Gap == aOther.m_Gap )
135  && ( m_ViaGap == aOther.m_ViaGap );
136  }
137 
138  bool operator<( const DIFF_PAIR_DIMENSION& aOther ) const
139  {
140  if( m_Width != aOther.m_Width )
141  return m_Width < aOther.m_Width;
142 
143  if( m_Gap != aOther.m_Gap )
144  return m_Gap < aOther.m_Gap;
145 
146  return m_ViaGap < aOther.m_ViaGap;
147  }
148 };
149 
150 
151 enum
152 {
158 
160 };
161 
162 
168 {
169 public:
170  // Note: the first value in each dimensions list is the current netclass value
171  std::vector<int> m_TrackWidthList;
172  std::vector<VIA_DIMENSION> m_ViasDimensionsList;
173  std::vector<DIFF_PAIR_DIMENSION> m_DiffPairDimensionsList;
174 
175  // List of netclasses. There is always the default netclass.
177 
181 
184 
185  // if true, when creating a new track starting on an existing track, use this track width
192 
193  // Global mask margins:
196  // 2 areas near than m_SolderMaskMinWidth
197  // are merged
200 
203 
204  // Arrays of default values for the various layer classes.
205  int m_LineThickness[ LAYER_CLASS_COUNT ];
206  wxSize m_TextSize[ LAYER_CLASS_COUNT ];
207  int m_TextThickness[ LAYER_CLASS_COUNT ];
208  bool m_TextItalic[ LAYER_CLASS_COUNT ];
209  bool m_TextUpright[ LAYER_CLASS_COUNT ];
210 
211  // Variables used in footprint editing (default value in item/footprint creation)
212 
213  wxString m_RefDefaultText;
214  // if empty, use footprint name as default
217  // should be a PCB_LAYER_ID, but use an int
218  // to save this param in config
219 
221  // if empty, use footprint name as default
224  // should be a PCB_LAYER_ID, but use an int
225  // to save this param in config
226 
227  // Miscellaneous
230 
232  // when importing values or create a new pad
233 
234 private:
235  // Indicies into the trackWidth, viaSizes and diffPairDimensions lists.
236  // The 0 index is always the current netclass value(s)
238  unsigned m_viaSizeIndex;
239  unsigned m_diffPairIndex;
240 
241  // Custom values for track/via sizes (specified via dialog instead of netclass or lists)
245 
246  // Custom values for differential pairs (specified via dialog instead of netclass/lists)
249 
251 
254 
257 
261 
262 public:
264 
269  inline NETCLASSPTR GetDefault() const
270  {
271  return m_NetClasses.GetDefault();
272  }
273 
278  inline const wxString& GetCurrentNetClassName() const
279  {
280  return m_currentNetClassName;
281  }
282 
287  inline bool UseNetClassTrack() const
288  {
289  return ( m_trackWidthIndex == 0 && !m_useCustomTrackVia );
290  }
291 
296  inline bool UseNetClassVia() const
297  {
298  return ( m_viaSizeIndex == 0 && !m_useCustomTrackVia );
299  }
300 
305  inline bool UseNetClassDiffPair() const
306  {
307  return ( m_diffPairIndex == 0 && !m_useCustomDiffPair );
308  }
309 
318  bool SetCurrentNetClass( const wxString& aNetClassName );
319 
324  int GetBiggestClearanceValue();
325 
330  int GetSmallestClearanceValue();
331 
337  int GetCurrentMicroViaSize();
338 
344  int GetCurrentMicroViaDrill();
345 
350  inline unsigned GetTrackWidthIndex() const { return m_trackWidthIndex; }
351 
358  void SetTrackWidthIndex( unsigned aIndex );
359 
366  inline int GetCurrentTrackWidth() const
367  {
368  return m_useCustomTrackVia ? m_customTrackWidth : m_TrackWidthList[m_trackWidthIndex];
369  }
370 
378  inline void SetCustomTrackWidth( int aWidth )
379  {
380  m_customTrackWidth = aWidth;
381  }
382 
387  inline int GetCustomTrackWidth() const
388  {
389  return m_customTrackWidth;
390  }
391 
396  inline unsigned GetViaSizeIndex() const
397  {
398  return m_viaSizeIndex;
399  }
400 
407  void SetViaSizeIndex( unsigned aIndex );
408 
415  inline int GetCurrentViaSize() const
416  {
417  if( m_useCustomTrackVia )
418  return m_customViaSize.m_Diameter;
419  else
420  return m_ViasDimensionsList[m_viaSizeIndex].m_Diameter;
421  }
422 
430  inline void SetCustomViaSize( int aSize )
431  {
432  m_customViaSize.m_Diameter = aSize;
433  }
434 
439  inline int GetCustomViaSize() const
440  {
441  return m_customViaSize.m_Diameter;
442  }
443 
450  int GetCurrentViaDrill() const;
451 
459  inline void SetCustomViaDrill( int aDrill )
460  {
461  m_customViaSize.m_Drill = aDrill;
462  }
463 
468  inline int GetCustomViaDrill() const
469  {
470  return m_customViaSize.m_Drill;
471  }
472 
480  inline void UseCustomTrackViaSize( bool aEnabled )
481  {
482  m_useCustomTrackVia = aEnabled;
483  }
484 
489  inline bool UseCustomTrackViaSize() const
490  {
491  return m_useCustomTrackVia;
492  }
493 
498  inline unsigned GetDiffPairIndex() const { return m_diffPairIndex; }
499 
504  void SetDiffPairIndex( unsigned aIndex );
505 
512  inline void SetCustomDiffPairWidth( int aWidth )
513  {
514  m_customDiffPair.m_Width = aWidth;
515  }
516 
522  {
523  return m_customDiffPair.m_Width;
524  }
525 
532  inline void SetCustomDiffPairGap( int aGap )
533  {
534  m_customDiffPair.m_Gap = aGap;
535  }
536 
541  inline int GetCustomDiffPairGap()
542  {
543  return m_customDiffPair.m_Gap;
544  }
545 
552  inline void SetCustomDiffPairViaGap( int aGap )
553  {
554  m_customDiffPair.m_ViaGap = aGap;
555  }
556 
562  {
563  return m_customDiffPair.m_ViaGap > 0 ? m_customDiffPair.m_ViaGap : m_customDiffPair.m_Gap;
564  }
565 
571  inline void UseCustomDiffPairDimensions( bool aEnabled )
572  {
573  m_useCustomDiffPair = aEnabled;
574  }
575 
580  inline bool UseCustomDiffPairDimensions() const
581  {
582  return m_useCustomDiffPair;
583  }
584 
591  inline int GetCurrentDiffPairWidth() const
592  {
593  if( m_useCustomDiffPair )
594  return m_customDiffPair.m_Width;
595  else
596  return m_DiffPairDimensionsList[m_diffPairIndex].m_Width;
597  }
598 
605  inline int GetCurrentDiffPairGap() const
606  {
607  if( m_useCustomDiffPair )
608  return m_customDiffPair.m_Gap;
609  else
610  return m_DiffPairDimensionsList[m_diffPairIndex].m_Gap;
611  }
612 
619  inline int GetCurrentDiffPairViaGap() const
620  {
621  if( m_useCustomDiffPair )
622  return m_customDiffPair.m_ViaGap;
623  else
624  return m_DiffPairDimensionsList[m_diffPairIndex].m_ViaGap;
625  }
626 
632  void SetMinHoleSeparation( int aDistance );
633 
638  void SetRequireCourtyardDefinitions( bool aRequire );
639 
644  void SetProhibitOverlappingCourtyards( bool aProhibit );
645 
651  inline LSET GetVisibleLayers() const
652  {
653  return m_visibleLayers;
654  }
655 
661  void SetVisibleAlls();
662 
668  inline void SetVisibleLayers( LSET aMask )
669  {
670  m_visibleLayers = aMask & m_enabledLayers;
671  }
672 
679  inline bool IsLayerVisible( PCB_LAYER_ID aLayerId ) const
680  {
681  // If a layer is disabled, it is automatically invisible
682  return (m_visibleLayers & m_enabledLayers)[aLayerId];
683  }
684 
691  void SetLayerVisibility( PCB_LAYER_ID aLayerId, bool aNewState );
692 
698  inline int GetVisibleElements() const
699  {
700  return m_visibleElements;
701  }
702 
708  inline void SetVisibleElements( int aMask )
709  {
710  m_visibleElements = aMask;
711  }
712 
721  inline bool IsElementVisible( GAL_LAYER_ID aElementCategory ) const
722  {
723  return ( m_visibleElements & ( 1 << GAL_LAYER_INDEX( aElementCategory ) ) );
724  }
725 
733  void SetElementVisibility( GAL_LAYER_ID aElementCategory, bool aNewState );
734 
740  inline LSET GetEnabledLayers() const
741  {
742  return m_enabledLayers;
743  }
744 
750  void SetEnabledLayers( LSET aMask );
751 
758  inline bool IsLayerEnabled( PCB_LAYER_ID aLayerId ) const
759  {
760  return m_enabledLayers[aLayerId];
761  }
762 
767  inline int GetCopperLayerCount() const
768  {
769  return m_copperLayerCount;
770  }
771 
777  void SetCopperLayerCount( int aNewLayerCount );
778 
785  void AppendConfigs( BOARD* aBoard, PARAM_CFG_ARRAY* aResult );
786 
787  inline int GetBoardThickness() const { return m_boardThickness; }
788  inline void SetBoardThickness( int aThickness ) { m_boardThickness = aThickness; }
789 
794  int GetLineThickness( PCB_LAYER_ID aLayer ) const;
795 
800  wxSize GetTextSize( PCB_LAYER_ID aLayer ) const;
801 
806  int GetTextThickness( PCB_LAYER_ID aLayer ) const;
807 
808  bool GetTextItalic( PCB_LAYER_ID aLayer ) const;
809  bool GetTextUpright( PCB_LAYER_ID aLayer ) const;
810 
811  int GetLayerClass( PCB_LAYER_ID aLayer ) const;
812 
813 private:
814  void formatNetClass( NETCLASS* aNetClass, OUTPUTFORMATTER* aFormatter, int aNestLevel,
815  int aControlBits ) const;
816 };
817 
818 #endif // BOARD_DESIGN_SETTINGS_H_
wxString m_RefDefaultText
Default ref text on fp creation.
int m_SolderMaskMargin
Solder mask margin.
Struct VIA_DIMENSION is a small helper container to handle a stock of specific vias each with unique ...
A list of parameters type.
bool m_ValueDefaultVisibility
Default value text visibility on fp creation.
int GetCurrentDiffPairWidth() const
Function GetCurrentDiffPairWidth.
VIATYPE_T m_CurrentViaType
(VIA_BLIND_BURIED, VIA_THROUGH, VIA_MICROVIA)
int GetVisibleElements() const
Function GetVisibleElements returns a bit-mask of all the element categories that are visible...
wxString m_currentNetClassName
Current net class name used to display netclass info.
bool operator<(const VIA_DIMENSION &aOther) const
NETCLASSPTR GetDefault() const
Function GetDefault.
wxPoint m_GridOrigin
origin for grid offsets
int m_SolderPasteMargin
Solder paste margin absolute value.
void SetCustomDiffPairViaGap(int aGap)
Function SetCustomDiffPairViaGap Sets custom via gap for differential pairs (i.e. ...
bool UseNetClassDiffPair() const
Function UseNetClassDiffPair returns true if netclass values should be used to obtain appropriate dif...
std::vector< int > m_TrackWidthList
bool m_ProhibitOverlappingCourtyards
check for overlapping courtyards in DRC
std::vector< DIFF_PAIR_DIMENSION > m_DiffPairDimensionsList
void SetCustomViaDrill(int aDrill)
Function SetCustomViaDrill Sets custom size for via drill (i.e.
void UseCustomDiffPairDimensions(bool aEnabled)
Function UseCustomDiffPairDimensions Enables/disables custom differential pair dimensions.
bool IsLayerEnabled(PCB_LAYER_ID aLayerId) const
Function IsLayerEnabled tests whether a given layer is enabled.
GAL_LAYER_ID
GAL layers are "virtual" layers, i.e.
bool operator==(const VIA_DIMENSION &aOther) const
The common library.
Class OUTPUTFORMATTER is an important interface (abstract class) used to output 8 bit text in a conve...
Definition: richio.h:327
int m_ValueDefaultlayer
Default value text layer on fp creation.
DIFF_PAIR_DIMENSION m_customDiffPair
bool IsLayerVisible(PCB_LAYER_ID aLayerId) const
Function IsLayerVisible tests whether a given layer is visible.
VIATYPE_T
Definition: class_track.h:50
void SetBoardThickness(int aThickness)
int GetCurrentViaSize() const
Function GetCurrentViaSize.
Struct DIFF_PAIR_DIMENSION is a small helper container to handle a stock of specific differential pai...
void SetCustomViaSize(int aSize)
Function SetCustomViaSize Sets custom size for via diameter (i.e.
int GetCustomDiffPairWidth()
Function GetCustomDiffPairWidth.
Functions relatives to tracks, vias and segments used to fill zones.
wxSize GetTextSize(const wxString &aSingleLine, wxWindow *aWindow)
Return the size of aSingleLine of text when it is rendered in aWindow using whatever font is currentl...
Definition: common.cpp:111
unsigned GetViaSizeIndex() const
Function GetViaSizeIndex.
void SetVisibleLayers(LSET aMask)
Function SetVisibleLayers changes the bit-mask of visible layers.
PCB_LAYER_ID
A quick note on layer IDs:
int m_HoleToHoleMin
Min width of peninsula between two drilled holes.
int GetCurrentDiffPairGap() const
Function GetCurrentDiffPairGap.
Class LSET is a set of PCB_LAYER_IDs.
int GetCopperLayerCount() const
Function GetCopperLayerCount.
Class NETCLASSES is a container for NETCLASS instances.
Definition: netclass.h:224
bool UseCustomDiffPairDimensions() const
Function UseCustomDiffPairDimensions.
const wxString & GetCurrentNetClassName() const
Function GetCurrentNetClassName.
#define GAL_LAYER_INDEX(x)
Use this macro to convert a GAL layer to a 0-indexed offset from LAYER_VIAS.
int GetCustomViaSize() const
Function GetCustomViaSize.
int m_TrackMinWidth
track min value for width ((min copper size value
bool UseNetClassTrack() const
Function UseNetClassTrack returns true if netclass values should be used to obtain appropriate track ...
void SetCustomDiffPairWidth(int aWidth)
Function SetCustomDiffPairWidth Sets custom track width for differential pairs (i.e.
int m_ViasMinSize
vias (not micro vias) min diameter
Class NETCLASS handles a collection of nets and the parameters used to route or test these nets...
Definition: netclass.h:55
int m_ViasMinDrill
vias (not micro vias) min drill diameter
bool m_BlindBuriedViaAllowed
true to allow blind/buried vias
int GetCustomViaDrill() const
Function GetCustomViaDrill.
wxString m_ValueDefaultText
Default value text on fp creation.
void SetCustomDiffPairGap(int aGap)
Function SetCustomDiffPairGap Sets custom gap for differential pairs (i.e.
int m_MicroViasMinSize
micro vias (not vias) min diameter
bool IsElementVisible(GAL_LAYER_ID aElementCategory) const
Function IsElementVisible tests whether a given element category is visible.
int GetCustomTrackWidth() const
Function GetCustomTrackWidth.
void SetCustomTrackWidth(int aWidth)
Function SetCustomTrackWidth Sets custom width for track (i.e.
Pad object description.
int GetCurrentDiffPairViaGap() const
Function GetCurrentDiffPairViaGap.
LSET m_visibleLayers
Bit-mask for layer visibility.
int m_visibleElements
Bit-mask for element category visibility.
bool m_RequireCourtyards
require courtyard definitions in footprints
unsigned GetDiffPairIndex() const
Function GetDiffPairIndex.
Class BOARD holds information pertinent to a Pcbnew printed circuit board.
Definition: class_board.h:170
int GetCustomDiffPairViaGap()
Function GetCustomDiffPairViaGap.
NETCLASSPTR GetDefault() const
Function GetDefault.
Definition: netclass.h:268
bool UseNetClassVia() const
Function UseNetClassVia returns true if netclass values should be used to obtain appropriate via size...
D_PAD m_Pad_Master
A dummy pad to store all default parameters.
void SetVisibleElements(int aMask)
Function SetVisibleElements changes the bit-mask of visible element categories.
int m_RefDefaultlayer
Default ref text layer on fp creation.
std::vector< VIA_DIMENSION > m_ViasDimensionsList
unsigned GetTrackWidthIndex() const
Function GetTrackWidthIndex.
DIFF_PAIR_DIMENSION(int aWidth, int aGap, int aViaGap)
VIA_DIMENSION(int aDiameter, int aDrill)
int m_copperLayerCount
Number of copper layers for this design.
bool m_MicroViasAllowed
true to allow micro vias
LSET GetEnabledLayers() const
Function GetEnabledLayers returns a bit-mask of all the layers that are enabled.
bool UseCustomTrackViaSize() const
Function UseCustomTrackViaSize.
int m_MicroViasMinDrill
micro vias (not vias) min drill diameter
double m_SolderPasteMarginRatio
Solder pask margin ratio value of pad size The final margin is the sum of these 2 values...
int GetCurrentTrackWidth() const
Function GetCurrentTrackWidth.
LSET GetVisibleLayers() const
Function GetVisibleLayers returns a bit-mask of all the layers that are visible.
bool operator<(const DIFF_PAIR_DIMENSION &aOther) const
bool operator==(const DIFF_PAIR_DIMENSION &aOther) const
LSET m_enabledLayers
Bit-mask for layer enabling.
bool m_RefDefaultVisibility
Default ref text visibility on fp creation.
wxPoint m_AuxOrigin
origin for plot exports
int m_boardThickness
Board thickness for 3D viewer.
int GetCustomDiffPairGap()
Function GetCustomDiffPairGap.
void UseCustomTrackViaSize(bool aEnabled)
Function UseCustomTrackViaSize Enables/disables custom track/via size settings.
int m_SolderMaskMinWidth
Solder mask min width.
Class BOARD_DESIGN_SETTINGS contains design settings for a BOARD object.